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Timing adjustment circuit and semiconductor integrated circuit device

A technology for timing adjustment and circuit generation, applied in electrical components, single output arrangement, automatic power control, etc., can solve problems such as difficulty in generating timing adjustment output signals and narrowing of the PFD's operable range.

Active Publication Date: 2018-07-06
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] In other words, when the frequency of the input signal (input clock signal) of the DLL circuit becomes higher, the operable range of the PFD narrows, so, for example, the PFD malfunctions at startup, which may make it difficult to generate timing-adjusted output signal

Method used

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  • Timing adjustment circuit and semiconductor integrated circuit device
  • Timing adjustment circuit and semiconductor integrated circuit device
  • Timing adjustment circuit and semiconductor integrated circuit device

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Embodiment Construction

[0034] First, before describing the embodiments of the timing adjustment circuit and the semiconductor integrated circuit device, reference will be made to Figure 1 to Figure 6C An example describing a timing adjustment circuit and its problematic points.

[0035] figure 1 is a block diagram depicting an example of a timing adjustment circuit (DLL circuit). exist figure 1 Here, reference numeral 1 denotes a voltage-controlled delay line (VCDL), reference numerals 101 to 112 denote delay units, and reference numerals 203 to 211 denote waveform shaping units. Further, reference numeral 3 denotes a phase frequency detector (PFD: Phase Detector), reference numeral 4 denotes a charge pump (CP), and reference numeral 5 denotes a capacitor.

[0036] like figure 1 As depicted in , VCDL 1 has a plurality of cascaded delay units 101 to 112 , and output signals of delay units 103 to 111 are output via corresponding waveform shaping units 203 to 211 , respectively.

[0037] For exam...

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PUM

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Abstract

A timing adjustment circuit includes a voltage-controlled delay line, a phase detector, a control voltage generating circuit, and a start-up circuit. The voltage-controlled delay line receives an input clock signal and generates multi-phase clocks, the amount of delay of each of the multi-phase clocks varies according to the control voltage. The phase detector detects a phase difference between a first clock, which is a reference clock, and a second clock, which is generated from a voltage-controlled delay line. The control voltage generating circuit generates a control voltage based on the detected phase difference. The startup circuit operates for a certain period of time after being activated, and continuously changes the control voltage between the first voltage and the second voltage.

Description

technical field [0001] Embodiments discussed herein relate to timing adjustment circuits and semiconductor integrated circuit devices. Background technique [0002] In recent years, the performance of semiconductor memories (eg, DRAM: Dynamic Random Access Memory), processors, and the like used in computers and other information processing apparatuses have been significantly improved. Therefore, it is preferable to correctly and promptly implement signal transmission between chips mounted on a circuit board and between a plurality of elements and circuit blocks within a chip. [0003] In view of this, for example, there is a known technique in which: a timing adjustment circuit (eg, a DLL circuit: a delay-locked loop circuit) is provided on the receiving side; a polyphase clock is generated by delaying an input clock signal passing through the DLL circuit ; and reading (determining) the data at appropriate timing. [0004] On the other hand, there is also known SerDes (ser...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/08H03K5/14
CPCH03L7/0807H03L7/0812H03L7/10H03L7/085
Inventor 松田笃
Owner SOCIONEXT INC