Semiconductor device and method for manufacturing the same

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of different depletion layer extensions and cannot be guaranteed at the same time, and achieve the effect of suppressing the drop in withstand voltage

Active Publication Date: 2015-05-27
MITSUBISHI ELECTRIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] Therefore, there is a problem that the expansion of the depletion layer differs between the straight portion and the corner portion, and the same withstand voltage (maximum withstand voltage) cannot be ensured at the same time in the str

Method used

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  • Semiconductor device and method for manufacturing the same
  • Semiconductor device and method for manufacturing the same
  • Semiconductor device and method for manufacturing the same

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0067] The semiconductor device D according to Embodiment 1 will be described. like Figure 4 , Figure 5 and Image 6 As shown, for the high voltage isolation region 16, the layout pattern has: a fan-shaped corner 18 with a central angle of about 90°, which is located along the corner pattern of the rectangular high-potential side circuit region 13; and The straight portion 17 is located along the straight line pattern. An N+ type diffusion layer 5 to which a high voltage is applied is formed in the high potential side circuit region 13 .

[0068] The impurity concentration of the N-type diffusion layer 3 b in the corner portion 18 is set to be approximately twice the impurity concentration of the N-type diffusion layer 3 a in the straight portion 17 . Accordingly, the number of atoms of impurities in the N-type diffusion layer 3b and the number of atoms of impurities in the predetermined volume of the N-type diffusion layer 3a become the same number, and it is possible t...

Embodiment approach 2

[0098] Here, a second example of introduction (implantation) distribution of impurities into the high withstand voltage isolation region in the main steps of the manufacturing method of the semiconductor device will be described.

[0099] like Figure 19 and Figure 20 As shown, a resist pattern 43 that exposes the corner portion 18 and the straight portion 17 and covers other regions is formed. Then, using the resist pattern 43 as an implantation mask, the N-type impurity 22a is implanted into the corner portion 18 and the straight portion 17 under the condition that the N-type diffusion layer 3b opposite to the corner portion 18 has an optimum impurity concentration. . Then, the resist pattern 43 is removed.

[0100] Next, if Figure 19 and Figure 21 As shown, a resist pattern 44 covering the corner portion 18 and exposing the straight portion 17 is formed. Then, the P-type impurity 22b is implanted into the straight portion 17 using the resist pattern 44 as an implanta...

Embodiment approach 3

[0104] Here, a third example of the introduction (implantation) distribution of impurities into the high withstand voltage isolation region in the main steps of the manufacturing method of the semiconductor device will be described.

[0105] like Figure 23 and Figure 24 As shown, a resist pattern 45 that exposes the corner portion 18 and the straight portion 17 and covers other regions is formed. Then, using the resist pattern 45 as an implantation mask, the N-type impurity 23a is implanted into the corner portion 18 and the straight portion 17 under the condition that the impurity concentration of the N-type diffusion layer 3a in the straight portion 17 is optimized. . Then, the resist pattern 45 is removed.

[0106] Next, if Figure 23 and Figure 25 As shown, a resist pattern 46 exposing the corner portion 18 and covering the straight portion 17 is formed. Then, N-type impurities 23b are additionally implanted into the corner portion 18 using the resist pattern 46 a...

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PUM

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Abstract

An N type diffusion layer in which a high-side circuit region is disposed is formed from a surface of a P type epitaxial layer covering a surface of a P type semiconductor substrate to reach the surface of the semiconductor substrate. An N type high breakdown voltage isolation region is formed with a prescribed width to surround high-side circuit region. High breakdown voltage isolation region includes a corner portion located along a corner pattern of rectangular high-side circuit region, and a linear portion located along a linear pattern thereof. The concentration of an impurity in an N type diffusion layer of corner portion is set to be higher than the concentration of an impurity in an N type diffusion layer of linear portion.

Description

technical field [0001] The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular, to a semiconductor device having a lateral high withstand voltage element and a method of manufacturing the semiconductor device. Background technique [0002] A drive circuit for operating a load such as an induction motor as a semiconductor device having a lateral high withstand voltage element will be described. The drive control circuit is provided with: a low-potential side circuit, which controls the switching operation of semiconductor elements such as IGBT (Insulated Gate Bipolar Transistor) based on the substrate potential; and a high-potential side circuit, which uses a higher potential than the substrate potential A predetermined potential (high voltage) is used as a reference to control the switching operation of the semiconductor element; and a potential conversion circuit performs signal transmission between the high potentia...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L29/36
CPCH01L21/26513H01L21/266H01L29/063H01L21/265H01L21/30604H01L21/308
Inventor 吉野学
Owner MITSUBISHI ELECTRIC CORP
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