33results about How to "Suppression of drop in withstand voltage" patented technology

A wide band gap semiconductor device is disclosed. A first trench in a gate electrode part and a second trench in a source electrode part (Schottky diode part) are disposed so that the first and second trenches are close to each other while and the second trench is deeper than the first trench. A metal electrode is formed in the second trench to form a Schottky junction on a surface of an n-type drift layer in the bottom of the second trench. Further, a p+-type region is provided in part of the built-in Schottky diode part being in contact with the surface of the n-type drift layer, preferably in the bottom of the second trench. The result is a wide band gap semiconductor device which is small in size and low in on-resistance and loss, and in which electric field concentration applied on a gate insulating film is relaxed to suppress lowering of withstand voltage to thereby increase avalanche breakdown tolerance at turning-off time.

A semiconductor device including: a first semiconductor layer having a first conductive type; a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer having a second conductive type that is a conductive type different from the first conductive type; an impurity region of the first conductive type formed at a surface of the second semiconductor layer; first electrodes contacting the impurity region, the second semiconductor layer, and the first semiconductor layer via a first insulating film; and second electrodes contacting the first electrodes via a second insulating film, and contacting the first semiconductor layer via a third insulating film, the second electrodes including PN junctions at borders between upper portions that contact the first semiconductor layer via the third insulating film and lower portions that contact the first semiconductor layer via the third insulating film.

A metal base substrate of the present invention includes a copper plate made of copper, a metal layer that is formed on the copper plate and is made of a metal different from the copper, an insulating resin sheet that is formed by bonding a sheet made of an insulating resin onto the metal layer, and a circuit pattern formed on the insulating resin sheet.

A semiconductor device may be provided with a semiconductor substrate, an insulating film disposed on a surface of the semiconductor substrate, at least one electrode disposed on a surface of the insulating film, and a voltage applying circuit configured to apply a first voltage to the at least one electrode. The semiconductor substrate may be provided with a cell region and a non-cell region adjacent to the cell region. The cell region is provided with a semiconductor element, and the non-cell region is provided with a withstand voltage structure. The insulating film may be disposed on a surface of the non-cell region. The at least one electrode may be electrically insulated from the semiconductor substrate. The voltage applying circuit may apply the first voltage to the electrode during at least a part of a first period in which a second voltage is not applied to the semiconductor element.

In a radiation generating apparatus of the present invention, a radiation tube in which a tubular side wall is arranged between a cathode and an anode is enclosed in an envelope filled with an insulating liquid. A thermally-conductive fin projecting to a side of a barrel portion of the radiation tube is provided on at least a part of an inner surface of the envelope, and the fin is provided on an area except for an area facing a position of the barrel portion at which potential of the barrel portion is higher than potential of the fin. Since a proper-shape cooling structure is provided on a proper position in the envelope, it is possible to secure withstand voltage and also made the entire apparatus compact in size.

In a semiconductor device having a trench-gate structure in which polysilicon doped with boron is embedded in a trench, insulating film formed on the inner wall of the trench comprises ONO film, and silicon nitride film constituting the ONO film is formed to such film thickness and film quality that boron can be suppressed from passing through the silicon nitride film. Silicon oxide film is formed so that a top oxide film is thin and a bottom oxide film is thick.

The photomultiplier tube 1 is provided with a casing 5 made of an upper frame 2 and a lower frame 4, an electron multiplying part 33 having dynodes 33a to 33l arrayed on the lower frame 4, a photocathode 41, and an anode part 34. Conductive layers 202 are installed on an opposing surface 20a of the upper frame 2. The electron multiplying part 33 is provided with base parts 52a to 52d of the respective dynodes 33a to 33d installed on the side of the lower frame 4, and power supplying parts 53a to 53d connected to the conductive layers 202 at one end parts of the respective base parts 52a to 52d in a direction along the opposing surface 40a. The base parts 52a to 52d are constituted in such a manner that the both end parts are joined to the opposing surface 40a, the central part is spaced away from the opposing surface 40a, and a cross sectional area at the one end part on the side of each of the power supplying parts 53a to 53d is made greater than a cross sectional area at another end part.

A semiconductor device including a well resistance element of high accuracy and high withstand voltage and a method of manufacturing the semiconductor device are provided.

The semiconductor device includes a semiconductor substrate, a well region, an input terminal, an output terminal, a separation insulating film, and an active region. The input terminal and the output terminal are electrically coupled to the well region. The separation insulating film is arranged to be in contact with the upper surface of the well region in an intermediate region between the input terminal and the output terminal. The active region is arranged to be in contact with the upper surface of the well region. The separation insulating film and the active region in the intermediate region have an elongated shape in plan view. In the intermediate region, a plurality of separation insulating films and a plurality of active regions are alternately and repeatedly arranged.

A power semiconductor device in an embodiment of the invention includes a high resistance epitaxial layer having a first pillar region and a second pillar region as a drift layer. The first pillar region includes a plurality of first pillars of the first conductivity type and a plurality of second pillars of the second conductivity type disposed alternately along a first direction. The second pillar region is adjacent to the first pillar region along the first direction. The second pillar region includes a third pillar and a fourth pillar of a conductivity type opposite to a conductivity type of the third pillar. A net quantity of impurities in the third pillar is less than a net quantity of impurities in each of the plurality of first pillars. A net quantity of impurities in the fourth pillar is less than the net quantity of impurities in the third pillar.

An N type diffusion layer in which a high-side circuit region is disposed is formed from a surface of a P type epitaxial layer covering a surface of a P type semiconductor substrate to reach the surface of the semiconductor substrate. An N type high breakdown voltage isolation region is formed with a prescribed width to surround high-side circuit region. High breakdown voltage isolation region includes a corner portion located along a corner pattern of rectangular high-side circuit region, and a linear portion located along a linear pattern thereof. The concentration of an impurity in an N type diffusion layer of corner portion is set to be higher than the concentration of an impurity in an N type diffusion layer of linear portion.

In a semiconductor substrate of a semiconductor device, a drift layer, a body layer, an emitter layer, and a trench gate electrode are formed. When the semiconductor substrate is viewed in a plane manner, the semiconductor substrate is divided into a first region covered with a heat dissipation member, and a second region not covered with the heat dissipation member. A density of trench gate electrodes in the first region is equal to a density of trench gate electrodes in the second region. A value obtained by dividing an effective carrier amount of channel parts formed in the first region by an area of the first region is larger than a value obtained by dividing an effective carrier amount of channel parts formed in the second region by an area of the second region.

An object of the present disclosure is to suppress decrease in withstand voltage and increase in ON voltage and to increase body diode current. An SiC-MOSFET includes: a source region formed on a surface layer of a base region; a gate electrode facing a channel region which is a region of the base region sandwiched between a drift layer and the source region via a gate insulating film; a source electrode having electrically contact with the source region; and a plurality of first embedded regions of a second conductivity type formed adjacent to a lower surface of the base region. The plurality of first embedded regions are formed immediately below at least both end portions of the base region, and three or more first embedded regions are formed to be separated from each other.

The invention provides a superjunction semiconductor device and a method of manufacturing the superjunction semiconductor device, which can restrain voltage resistance reduction caused by manufacturing deviation. The semiconductor device has an active region (30) through which current flows and a termination structure region (40). On a front surface of a semiconductor substrate (1) of a first conductivity type, a first semiconductor layer (2) of the first conductivity type is provided. On a surface of the first semiconductor layer (2) in the active region (30), a first parallel pn structure isprovided including first columns (3a) of the first conductivity type and second columns (4a) of a second conductivity type disposed repeatedly alternating one another in a plane parallel to the frontsurface. In the termination structure region (40), a second parallel pn structure is provided including third columns (3b) of the first conductivity type and fourth columns (4b) of the second conductivity type disposed repeatedly alternating one another. On a surface of the second parallel pn structure, a first semiconductor region (17) of the second conductivity type is provided including pluralregions apart from one another.

An object of a technique of the present disclosure is to suppress reduction in withstand voltage in a power semiconductor device. A semiconductor base includes an n− type semiconductor substrate and at least one p type diffusion layer formed separately from each other on a surface layer on a side of a first main surface of the semiconductor substrate in a terminal region. A power semiconductor device includes at least one insulating film formed on a first main surface of the semiconductor base between an insulating film and the insulating film. A semi-insulating film has contact with the insulating film on the insulating film, and has contact with the first main surface in at least two regions where the insulating film is not formed between the insulating films and.