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Power semiconductor device

A semiconductor and power technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems of impurity injection amount deviation, withstand voltage reduction, etc., and achieve the effect of suppressing withstand voltage reduction

Inactive Publication Date: 2013-04-03
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, in the case of a superstructure structure, due to variations in the amount of impurity implanted in the manufacturing process, the withstand voltage tends to decrease in the termination region compared to the element region of a power semiconductor device.

Method used

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no. 1 Embodiment approach

[0028] use Figure 1 to Figure 5 , the power semiconductor device according to the first embodiment of the present invention will be described. figure 1 It is a schematic sectional view of main parts of the power semiconductor device according to the first embodiment. figure 2 It is a figure which shows a part of the manufacturing process of the power semiconductor device of 1st Embodiment, (a) is a main part schematic cross-sectional view, (b) is an enlarged view of A part in (a), (c) is ( a) Schematic cross-sectional view of the main part of the subsequent process. image 3 It is a figure showing a part of the manufacturing process of the power semiconductor device of 1st Embodiment, (a) is a main part schematic cross-sectional view, (b) is a main part schematic cross-sectional view of the process after (a). Figure 4 It is a figure which shows a part of the manufacturing process of the power semiconductor device of a comparative example, and is the same as figure 2 (b)...

no. 2 Embodiment approach

[0068] use Figure 6 as well as Figure 7 , the power semiconductor device 200 of the second embodiment will be described. Figure 6 It is a schematic cross-sectional view of a main part of a power semiconductor device according to a second embodiment. Figure 7 It is a figure which shows part of the manufacturing process of the power semiconductor device of 2nd Embodiment, (a) is a main part schematic cross-sectional view, (b) is an enlarged view of the F part in (a). In addition, the same reference numerals or signs are assigned to the same configurations as those described in the first embodiment, and description thereof will be omitted. Differences from the first embodiment will be mainly described.

[0069] Such as Figure 6 As shown, the MOSFET 200 of the second embodiment, like the MOSFET 100 of the first embodiment, includes a high-resistance epitaxial layer 2 having a first pillar region and a second pillar region as n - shape drift layer. In the second column r...

no. 3 Embodiment approach

[0078] use Figure 8 as well as Figure 9 , the power semiconductor device 300 of the third embodiment will be described. Figure 8 It is a schematic sectional view of a main part of a power semiconductor device according to a third embodiment. Figure 9 It is a figure which shows part of the manufacturing process of the power semiconductor device of 3rd Embodiment, (a) is a main part schematic cross-sectional view, (b) is an enlarged view of G part in (a). In addition, the same reference numerals or symbols are assigned to the same components as those described in the first embodiment, and description thereof will be omitted. Differences from the first embodiment will be mainly described.

[0079] Such as Figure 8 As shown, the MOSFET 300 of the third embodiment, like the MOSFET 100 of the first embodiment, includes a high-resistance epitaxial layer 2 having a first pillar region and a second pillar region as n - shape drift layer. The second column region of the MOSFE...

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Abstract

A power semiconductor device in an embodiment of the invention includes a high resistance epitaxial layer having a first pillar region and a second pillar region as a drift layer. The first pillar region includes a plurality of first pillars of the first conductivity type and a plurality of second pillars of the second conductivity type disposed alternately along a first direction. The second pillar region is adjacent to the first pillar region along the first direction. The second pillar region includes a third pillar and a fourth pillar of a conductivity type opposite to a conductivity type of the third pillar. A net quantity of impurities in the third pillar is less than a net quantity of impurities in each of the plurality of first pillars. A net quantity of impurities in the fourth pillar is less than the net quantity of impurities in the third pillar.

Description

[0001] Cross References to Related Applications [0002] This application is based on and claims priority from prior Japanese Patent Application No. 2011-206341 filed on September 21, 2011, the entire contents of which are hereby incorporated by reference. technical field [0003] The present invention relates to a power semiconductor device having a superstructure structure in a drift layer. Background technique [0004] Power semiconductor devices generally have a vertical structure through which current flows in the vertical direction, and low power consumption is required together with high withstand voltage. As power semiconductor devices, there are, for example, MOSFET (Metal Oxide Semiconductor Field Effect Transistor, Metal Oxide Semiconductor Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor, Insulated Gate Bipolar Transistor), and IEGT (Injection Enhanced Gate Transistor, injection enhancement gate transistors), etc. In order to reduce power consu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/06
CPCH01L29/404H01L29/66712H01L29/7395H01L29/7811H01L29/0619H01L29/0623H01L29/0638H01L29/0878H01L29/1095
Inventor 大田浩史角保人木村淑铃木纯二入船裕行斋藤涉
Owner KK TOSHIBA
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