Novel semiconductor anti-shedding encapsulation structure

Abstract

The invention discloses a novel semiconductor anti-shedding encapsulation structure which comprises a substrate and a semiconductor chip installed on the upper surface of the substrate. A welding pad is arranged on the upper surface of the substrate, an encapsulating card block is welded on the welding pad which is electrically connected with the encapsulating card block, the encapsulating card block is electrically connected with the semiconductor chip through a lead, the substrate, the semiconductor chip, the welding pad, and the encapsulating card block and the lead are wrapped and covered through an encapsulating material. The conductive encapsulating clamp block is arranged on the welding pad, a drag hook is formed between the encapsulating material and the substrate, the substrate and the encapsulating material can be effectively ensured to bear various differential stress, shedding never occurs, encapsulation size is not increased, and the novel semiconductor anti-shedding encapsulating structure is quite convenient to machine and economical and suitable.

Description

technical field [0001] The invention relates to a semiconductor package structure, in particular to a semiconductor drop-off prevention package structure. technical background [0002] Nowadays, electronic products tend to be multi-functional and miniaturized, and the circuit components matched with them are correspondingly developing in the direction of miniaturization. In the existing substrate packaging structure, for example: the packaging structure with a substrate includes ball grid array packaging structure (BGA), pin grid array packaging structure (PGA), land grid array packaging structure (LGA) or chip-on-substrate packaging structure (BOC) etc. In the above packaging structure, at least one chip is carried on the upper surface of the substrate, and the several pads of the chip are electrically connected to the several pads of the upper surface of the substrate by wire bonding or bumping process, so It is also necessary to provide a large number of soldering pads ...

AI Technical Summary

Problems solved by technology

In the above packaging structure, at least one chip is carried on the upper surface of the substrate, and the several pads of the chip are electrically connected to the several pads of the upper surface of the substrate by wire bonding or bumping process, so It is also necessary to provide a large number of soldering pads on the lower surface of the above-mentioned substrate to solder several output solder balls. In the existing semiconductor substrate packaging structure, there is a certain degree of difference in the stress coefficient (such as thermal expansion coefficient) between the substrate and the encapsulant. When the package structure of the semiconductor substrate is subjected to stress changes (such as thermal expansion and contraction), the bonding interface between the two may be detached, especially the welding pads in the packaging compound and the solder joints of the wires ( or other stress concentration areas) are damaged by stress pulling, thus making the product fail

Images