Circuit structure of first-in-first-out memory based on random access memory

Abstract

The invention provides a first-in-first-out memory circuit structure based on a random access memory, relates to the field of chip design, constructs a multi-input single-output FIFO structure, and uses at least three ordinary single-access interface RAM storage bodies to construct a multi-access interface RAM memory bank, set configurable sorting mode, set independent read and write FIFO pointers, realize FIFO overflow error flag according to the vector flag bit corresponding to the address when writing, and realize FIFO overflow error flag according to the vector flag corresponding to the address when reading Bit no flag implements output FIFO underflow error flag. Using a new FIFO structure, it is possible to directly write multiple channels of messages into the FIFO in parallel, and then automatically sort them according to the set mode, serially output from the FIFO, and automatically complete the two functions of parallel storage and serial scheduling.

Description

technical field [0001] The invention relates to the field of chip design, in particular to a fast implementation method for parallel scheduling of data paths in the circuit implementation process of network control protocol chips in a multi-node network. Background technique [0002] With the continuous development of the server application field, the application requirements of high-end servers have entered an important stage. The realization of complex architecture supports high-end server systems to achieve high performance indicators, high security, high availability, and high reliability. This requires a network control chip to control the multi-processor system, so that the internal message transmission of the system can be efficient, reliable, safe and stable. For the design of this type of control chip, efficient scheduling of multi-channel high-speed packets is very necessary. In this case, the scheduling of multi-channel high-speed packets generally requires an a...

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Problems solved by technology

This makes the whole design process complicated, increases the design structure links, complicates the timing and functions, and increases the delay in some cases, thus complicating the circuit implementation process of the entire system, increasing the processing links, and increasing the delay. The difficulty increases, and the complexity of the entire chip design increases exponentially

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