Circuit structure of first-in-first-out memory based on random access memory

A circuit structure, first-in-first-out technology, applied in the field of rapid implementation of parallel scheduling, can solve the problems of increased design structure links, increased processing links, increased delays, etc., to reduce design complexity, speed up processing procedures, and reduce data delays Effect

CN104778025BActive Publication Date: 2017-12-01LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Publication Date
2017-12-01

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Abstract

The invention provides a first-in-first-out memory circuit structure based on a random access memory, relates to the field of chip design, constructs a multi-input single-output FIFO structure, and uses at least three ordinary single-access interface RAM storage bodies to construct a multi-access interface RAM memory bank, set configurable sorting mode, set independent read and write FIFO pointers, realize FIFO overflow error flag according to the vector flag bit corresponding to the address when writing, and realize FIFO overflow error flag according to the vector flag corresponding to the address when reading Bit no flag implements output FIFO underflow error flag. Using a new FIFO structure, it is possible to directly write multiple channels of messages into the FIFO in parallel, and then automatically sort them according to the set mode, serially output from the FIFO, and automatically complete the two functions of parallel storage and serial scheduling.
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Description

technical field

[0001] The invention relates to the field of chip design, in particular to a fast implementation method for parallel scheduling of data paths in the circuit implementation process of network control protocol chips in a multi-node network. Background technique

[0002] With the continuous development of the server application field, the application requirements of high-end servers have entered an important stage. The realization of complex architecture supports high-end server systems to achieve high performance indicators, high security, high availability, and high reliability. This requires a network control chip to control the multi-processor system, so that the internal message transmission of the system can be efficient, reliable, safe and stable. For the design of this type of control chip, efficient scheduling of multi-channel high-speed packets is very necessary. In this case, the scheduling of multi-channel high-speed packets generally requires an a...

Examples

Embodiment Construction

[0016] Referring to the accompanying drawings, a brief description will be given below of the implementation of the content of the present invention.

[0017] Taking the currently designed high-speed network protocol chip as an example, in the design, after the multi-channel message data is received in parallel through the interface module, it enters the protocol processing module at the same time, and the multi-channel input and single-output FIFO is used for receiving and sorting, and then sequentially output to the Protocol processing module. Here, taking a FIFO with 2 channels of input and 1 channel of output as an example, the circuit structure and operation mode of this type of FIFO design are explained: when two channels of messages arrive at the FIFO at the same time and the FIFO read data signal is enabled at the same time, the FIFO simultaneously receives For the two-way message data, first obtain the writable address information in the current RAM according to the w...