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Shift register, gate drive circuit and liquid crystal display panel

A shift register and gate technology, applied in static memory, digital memory information, instruments, etc., can solve the problem of affecting the output capability of the gate drive circuit of the shift register, the large layout area of ​​the voltage stabilizing capacitor, and the disadvantage of meeting the narrow frame of the user In order to achieve the effect of reducing the layout area, satisfying the narrow border, and improving the output capacity

Active Publication Date: 2018-07-20
KUSN INFOVISION OPTOELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Then, the voltage stabilizing capacitor C1 is set on the clock signal line of each stage of the shift register, which not only affects the output capability of the shift register and the entire gate drive circuit, but also requires a large layout area to make the above voltage stabilizing capacitor. It is not conducive to meeting the user's demand for narrow borders

Method used

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  • Shift register, gate drive circuit and liquid crystal display panel
  • Shift register, gate drive circuit and liquid crystal display panel
  • Shift register, gate drive circuit and liquid crystal display panel

Examples

Experimental program
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Effect test

Embodiment 1

[0039]An embodiment of the present invention provides a shift register, figure 2 For the circuit structure diagram of the shift register provided in Embodiment 1 of the present invention, see figure 2 , the shift register includes a pull-up module 21, a pull-up drive module 22, a reset module 23, a pull-down module 24 and a voltage stabilizing module 25;

[0040] The pull-up module 21 includes a pull-up transistor M1, the source of the pull-up transistor M1 is electrically connected to the first clock signal line CLK1, the drain of the pull-up transistor M1 is electrically connected to the signal output end of the shift register, and the pull-up transistor M1 The gate of is electrically connected to the pull-up control node Q;

[0041] The output terminal of the pull-up driving module 22 is electrically connected to the pull-up control node Q, and is used to control the pull-up transistor M1 to turn on and output the scan signal;

[0042] The output terminal of the reset m...

Embodiment 2

[0047] image 3 The circuit structure of the shift register provided for the second embodiment of the present invention Figure 1 ,Such as image 3 As shown, on the basis of Embodiment 1, the voltage stabilizing module of the shift register further includes a third voltage stabilizing transistor M4, the gate of the third voltage stabilizing transistor M4 is electrically connected to the drain of the first voltage stabilizing transistor M2, The source of the third voltage stabilizing transistor M4 is electrically connected to the first clock signal line CLK1 , and the drain of the third voltage stabilizing transistor M4 is electrically connected to the voltage stabilizing control node QB. The third voltage stabilizing transistor cooperates with the first voltage stabilizing transistor to control the potential on the voltage stabilizing control node QB to be consistent with the signal of the first clock signal line in the stable output stage.

[0048] further, Figure 4 The c...

Embodiment 3

[0051] In the third embodiment, the specific circuits of the pull-up driving module, the pull-down module and the reset module involved in the above-mentioned embodiments will be described.

[0052] Figure 5 The circuit structure diagram of the shift register provided for the third embodiment of the present invention, such as Figure 5 As shown, the pull-up drive module 22 includes a pull-up drive transistor M7, the gate of the pull-up drive transistor M7 is electrically connected to the signal output terminals of the first two stages of shift registers, and the input scan signal Gn-2 is used as the shift register of this stage. The trigger signal of the register, and the source of the pull-up driving transistor M7 is electrically connected to the second clock signal line CLK2, and the drain of the pull-up driving transistor M7 is electrically connected to the pull-up control node Q;

[0053] The reset module 23 includes a reset transistor M8, the gate of the reset transisto...

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Abstract

The invention discloses a shift register, a grid driving circuit and a liquid crystal display panel. The shift register comprises a pull-up module, a pull-down module, a pull-up driving module, a reset module and a voltage stabilizing module. The voltage stabilizing module comprises a first voltage stabilizing transistor and at least one second voltage stabilizing transistor, the grid electrode and the source electrode of the first voltage stabilizing transistor are electrically connected with a first clock signal line, the drain electrode of the first voltage stabilizing transistor is electrically connected with a voltage stabilizing control node, the grid electrode of the second voltage stabilizing transistor is electrically connected with the voltage stabilizing control node, the source electrode of the second voltage stabilizing transistor is electrically connected with a voltage stabilizing signal line, and the drain electrode of the second voltage stabilizing transistor is electrically connected with a pull-up control node. The technical scheme provided by the invention can effectively improve the output capabilities of the shift register and the whole grid driving circuit.

Description

technical field [0001] The invention relates to the field of display technology, in particular to a shift register, a gate drive circuit and a liquid crystal display panel. Background technique [0002] Recently, with the development of liquid crystal display technology, the application of liquid crystal display panels is becoming more and more extensive. When the liquid crystal display panel is working, the gate drive circuit located in the liquid crystal display panel needs to generate scanning signals to drive each scanning line in the array substrate one by one, so that the data signal can be transmitted to each pixel unit in the array substrate. The above scan signal is generated by the shift register in the gate drive circuit. [0003] The gate drive circuit is mainly arranged in the non-display area of ​​the liquid crystal display panel. With the demand for narrow frame design, it is required that the layout area occupied by the gate drive circuit be as small as poss...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G09G3/36G11C19/28
Inventor 刘立伟秦刚朱欢欢
Owner KUSN INFOVISION OPTOELECTRONICS
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