Integrated circuit comprising components, for example nmos transistors, having active regions with relaxed compressive stresses

Abstract

An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from French application for patent No. 1451616 filed February 28, 2014, the disclosure of which is incorporated herein by reference. technical field [0003] The present invention relates to integrated circuits, and more particularly to relaxation of compressive stress in active regions, such as relaxation of compressive stress in active regions of NMOS transistors. Background technique [0004] In an integrated circuit, transistors are fabricated in and on an active semiconductor region, such as silicon, surrounded by an electrically insulating region, such as a trench filled with, for example, silicon dioxide. [0005] The fabrication of MOS transistors within an insulating region inherently leads to obtaining an active area which is compressively stressed due to the presence of the insulating region at its periphery. Furthermore, while a compressively stressed active region boosts ...

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Problems solved by technology

Furthermore, although the compressively stressed active region boosts the performance of PMOS transistors, it conversely causes degradation of the performance of NMOS transistors, especially in terms of carrier mobility

[0006] Furthermore, the fabrication of high-speed transistors requires small channel lengths and widths, and structures are often fabricated with high densities, which results in very small or even minimal active area dimensions for the technology in question

[0007] It is therefore very difficult or even impossible to increase the size of the active regions of NMOS transistors for the purpose of relaxing their compressive stresses, for the purpose of a desired density of the fabricated structures

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