Page management method based on embedded system mixed main memory

Abstract

The invention discloses a page management method based on an embedded system mixed main memory. The embedded system mixed main memory is an embedded system PCM / DRAM mixed main memory, a CPU of an embedded system sends an access page request, an access of the main memory is performed if request data or an instruction is not in a cache, and the page management method is executed at the moment. The page management method comprises building a CLOCK linked list existing in a page of the mixed main memory and an LRU linked list stored data of which are metadata of the page of an internal memory removed from the CLOCK linked list, determining whether the page accessed by the request is stored in the mixed main memory of the embedded system, accessing the CLOCK linked list if the page accessed by the request is stored in the mixed main memory of the embedded system, determining a type of the page in the CLOCK linked list to perform change operation of page identification bit or page migration operation, entering the next step if the page accessed by the request is not stored in the mixed main memory of the embedded system, obtaining a free page as a storage space of the accessed page, accessing the LRU linked list, and calling a page insertion algorithm to insert the accessed page into the mixed main memory.

Description

technical field [0001] The invention relates to a page management method, in particular to a page management method based on mixed main memory of an embedded system. Background technique [0002] In the era of big data, with the emergence and popularity of multi-core systems and new applications, computer system models have gradually evolved from computing-driven to data-driven. Therefore, large-capacity memory is the key to ensuring the performance of the entire computer system. However, traditional DRAM-based memory density is difficult to achieve very large. Studies have shown that the density of the future DRAM process will not be less than 22nm. In addition, the working mechanism of DRAM determines that it must be refreshed within a certain interval (2ms). These additional refresh operations are independent of data storage, but their energy consumption accounts for more than 70% of the entire DRAM energy consumption in most applications. As a result, traditional DRA...

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Problems solved by technology

[0008] (4) Anti-interference: Traditional DRAM memory needs to use capacitors as storage units, and capacitors will have withstand voltage problems. If the voltage exceeds the rated voltage, the capacitor will be damaged

[0011] (2) Long write delay: due to the change of crystal material state, it needs to be maintained for a long time

Therefore, compared to traditional DRAM, PCM takes longer to write data into memory cells

[0012] (3) Higher dynamic energy consumption: The write operation of PCM requires strong current heating and rapid quenching to change the state of the crystal material, so that the power consumption of the write operation is much higher than that of the read operation.

[0020] For example, when the number of writes of PCM pages exceeds how many times, it is migrated to DRAM; for different applications, the values ​​of these parameters are often difficult to determine

[0021] (3) Cannot effectively predict frequently written pages:

[0022] When the policy detects that a PCM page is frequently written, it will be migrated to DRAM, but the page will no longer be written, which will cause a wrong migration; or when the policy detects that a DARM page is rarely written, it will be migrated to PCM, but the page is often written thereafter and can also cause false migrations

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