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A Reliability Evaluation Method for Multi-Abstract Level Circuits

An abstract level and reliable technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., to achieve low cost, avoid rapid expansion, and avoid unreliable results

Active Publication Date: 2017-12-29
ZHEJIANG UNIV OF TECH
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Problems solved by technology

[0005] In order to overcome the defects that the existing technology is difficult to balance the evaluation accuracy and computational complexity, and cannot be applied to the reliability evaluation of circuits at different levels of abstraction, the present invention provides an iterative probability transfer based on a mixed coding mechanism combining binary and decimal Matrix method for high-accuracy and fast reliability evaluation of circuits with different levels of abstraction

Method used

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  • A Reliability Evaluation Method for Multi-Abstract Level Circuits

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Embodiment Construction

[0024] Referring to the attached picture:

[0025] A kind of reliability evaluation method for multi-abstraction level circuit of the present invention, comprises the following steps:

[0026] Step 1: Netlist analysis and initialization of related quantities.

[0027] 1) Read the circuit netlist.

[0028] 2) Detect the interconnection structure between the basic components of the circuit, and display the implicit series-parallel relationship; then implement layering on the circuit, and extract its original input terminal number (indicated by n) and original output terminal number (indicated by m).

[0029] 3) Extract the i-th original input signal of the circuit, and construct its probabilistic transfer matrix (PTM) based on mixed coding (using PMs i representation), the ideal transfer matrix (ideal transfermatrix, ITM) (using IMs i Represented) and the input probability distribution (with pds i express).

[0030] Among them, i refers to the serial number of the original in...

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Abstract

A reliability evaluation method for circuits with multiple levels of abstraction, including: step 1: netlist analysis and initialization of related quantities; step 2: iterative propagation of reliability of basic circuit components; step 3: outputting circuit reliability as a design basis .

Description

technical field [0001] The invention relates to the technical field of circuit reliability assessment, in particular to a circuit structure reliability assessment method based on an analytical model. technical background [0002] At present, with the introduction of new materials, new processes and new device structures, the silicon semiconductor industry still maintains the rapid development trend of Moore's Law. However, with the rapid development of integrated circuit technology, the reduction of the feature size of semiconductor devices, the reduction of power supply voltage, the increase of frequency, the increase of circuit density and the increase of complexity have caused the circuit chip to be sensitive to voltage disturbance, electromagnetic interference and radiation. All kinds of noise disturbances become more sensitive, which makes the reliability margin of the circuit drop sharply, and causes the usual worst-case design method to become unreliable due to the un...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 肖杰李伟杨旭华胡海根
Owner ZHEJIANG UNIV OF TECH
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