135results about How to "Reduce thickness variation" patented technology

Various embodiments of the present invention relate to a method for forming at a three-dimensional article through successively depositing individual layers of powder material that are fused together with at least one energy beam so as to form the article, said method comprising the steps of generating a model of said three-dimensional article; applying a first powder layer on a work table; directing said at least one energy beam from at least one energy beam source over said work table causing said first powder layer to fuse in first selected locations according to said model to form a first cross section of said three-dimensional article; introducing a predetermined pattern laterally separated from said first cross section for reducing thickness variations in a powder layer provided on top of said first cross section.

An electronic part-incorporated multilayer substrate is provided. The multi-layer substrate includes a core formed with a plurality of holes capable of containing an electronic part, a bottom insulating resin layer formed on a bottom surface of the core, a top insulating resin layer formed on a top surface of the core, a wiring layer selectively formed on an outer surface of the bottom insulating resin layer or top insulating resin layer, and an electronic part contained in any of the holes.Both of the bottom and top insulating resin layers have a structure that is a combination of a resin which is changed to cohesiveness when heated and which undergoes smaller plastic deformation when heated to a higher temperature and an insulating resin layer which has a thickness sufficient to maintain insulation between the electronic part or a conductor of the core and the wiring layer and which inherently undergoes small plastic deformation. Thus, the electronic part can be securely and sealed in the hole without using an adhesive separately.

A method for manufacturing a wiring board with built-in component. The method provides a secure connection between a component and interlayer insulating layers so that the wiring board with built-in component has excellent reliability. The wiring board is manufactured through a core board preparation step, a component preparation step, an accommodation step and a height alignment step. In the core board preparation step, a core board having an accommodation hole therein is prepared. In the component preparation step, a ceramic capacitor having therein a plurality of protruding conductors which protrudes from a capacitor rear surface is prepared. In the accommodation step, the ceramic capacitor is accommodated in the accommodation hole with the core rear surface facing the same side as the capacitor rear surface. In the height alignment step, a surface of a top portion of the protruding conductor and a surface of a conductor layer formed on the core rear surface are aligned to the same height.

The present invention discloses a resonator gyroscope comprising a resonator including two bodies, each with a center of mass and transverse inertia symmetry about an axis that are substantially coincident and each supported by one or more elastic elements and wherein the bodies together forming two differential rocking modes of vibration transverse to the axis with substantially equal frequencies and wherein the two bodies transfer substantially no net momentum to the baseplate when the resonator is excited. The gyroscope further includes a baseplate affixed to the resonator by the one or more elastic elements and sense and drive elements each affixed to the resonator and baseplate.

A method of reducing oxide thickness variations in a STI pattern that includes both a dense trench array and a wide trench is described. A first HDP CVD step with a deposition / sputter (D / S) ratio of 9.5 is used to deposit a dielectric layer with a thickness that is 120 to 130% of the shallow trench depth. An etch back is performed in the same CVD chamber with NF3, SiF4 or NF3 and SiF4 to remove about 40 to 50% of the initial dielectric layer. A second HDP CVD step with a D / S ratio of 16 deposits an additional thickness of dielectric layer to a level that is slightly higher than after the first deposition. The etch back and second deposition form a smoother dielectric layer surface which enables a subsequent planarization step to provide filled STI features with a minimal amount of dishing in wide trenches.

A hermetically sealed glass package preform is provided comprising a glass substrate; a frit comprising 65-100 wt. % of a base glass and about 0-35 wt. % of a filler; wherein the base glass comprises: about 0-5 mole % K2O; about 0-35 mole % Sb2O3; about 0-20 mole % ZnO; about 10-40 mole % P2O5; about 10-60 mole % V2O5; about 0-5 mole % TiO2; about 0-5 mole % B2O3; about 0-5 mole % SiO2; about 0-5 mole % WO3; and about 1-10 mole % of a metal oxide selected from the group consisting of Fe2O3, Nd2O3, La2O3, Ce2O4, Pr6O11, Er2O3, and CeO2; wherein the base glass has a mean particle size distribution of less than about 3 μm; and wherein the filler has a mean particle size distribution of between about 3 and 7 μm. The frit is sintered in an atmosphere less oxidizing than air at a temperature of between about 390° C. to 415° C.

A simple, effective and economical method to improved the yield of CMOS devices using contact etching stopper liner, including, single neutral stressed liner, single stressed liner and dual stress liner (DSL), technology is provided. In order to improve the chip yield, the present invention provides a method in which a sputter etching process is employed to smooth / flatten (i.e., thin) the top surface of the contact etch stopper liners. When DSL technology is used, the inventive sputter etching process is used to reduce the complexity caused by DSL boundaries to smooth / flatten top surface of the DSL, which results in significant yield increase. The present invention also provides a semiconductor structure including at least one etched liner.

A multilayer ceramic electronic device includes a laminated body having alternately laminated internal electrode layers and dielectric layers. The dielectric layer has a thickness of 0.5 μm or less. The internal electrode layers contain ceramic particles. A content ratio of the ceramic particles contained in the internal electrode layer is 2 to 15% by representation of cross sectional area.

A hermetically sealed glass package preform is provided comprising a glass substrate; a frit comprising 65-100 wt. % of a base glass and about 0-35 wt. % of a filler; wherein the base glass comprises: about 0-5 mole % K2O; about 0-35 mole % Sb2O3; about 0-20 mole % ZnO; about 10-40 mole % P2O5; about 10-60 mole % V2O5; about 0-5 mole % TiO2; about 0-5 mole % B2O3; about 0-5 mole % SiO2; about 0-5 mole % WO3; and about 1-10 mole % of a metal oxide selected from the group consisting of Fe2O3, Nd2O3, La2O3, Ce2O4, Pr6O11, Er2O3, and CeO2; wherein the base glass has a mean particle size distribution of less than about 3 μm; and wherein the filler has a mean particle size distribution of between about 3 and 7 μm. The frit is sintered in an atmosphere less oxidizing than air at a temperature of between about 390° C. to 415° C.

Managing pressure within a thickness-control-zone (muffle door) housing (20) relative to pressures in a glass-making machine enclosure (60) and an upper chamber (40)—that is disposed outside the enclosure—so as to minimize or control undesired airflows that would adversely affect thickness (9) of glass ribbon (8). According to one pressure-management technique, the pressure at a location (25) in the housing (20) is managed so as to be less than the pressure at a location (65) that is within the enclosure (60) as well as both outside and adjacent to the housing. In the event of a leak, as by a crack or unintended opening in the housing, for example, this pressure difference reduces or prevents airflow toward the ribbon and, thereby, undesired thickness variation in the ribbon. According to a second pressure-management technique, the pressure at location (25) is managed so as to be greater than the pressure in the upper chamber.

In a multi-layer substrate including a core formed with a plurality of holes capable of containing an electronic part, a bottom insulating resin layer formed on a bottom surface of the core, a top insulating resin layer formed on a top surface of the core, a wiring layer selectively formed on an outer layer of the bottom insulating resin layer or top insulating resin layer, and an electronic part contained in the holes, both of the bottom and top insulating resin layers have a structure that is a combination of a resin which is changed to cohesiveness when heated and which undergoes smaller plastic deformation when heated to a higher temperature and an insulating resin layer which has a thickness sufficient to maintain insulation between the electronic part or a conductor of the core and the wiring layer and which inherently undergoes small plastic deformation, so that the electronic part can be securely and sealed in the holes without using a particular adhesive.

A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source / drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented.

There is provided a multilayer ceramic electronic component including: a ceramic main body; a plurality of internal electrodes; and external electrodes formed on outer surfaces of the ceramic main body and electrically connected to the internal electrodes, wherein an average thickness of the external electrodes is 10 μm or less, and when a thickness of the external electrodes in a central portion of the ceramic main body in a thickness direction is Tc and a thickness of the external electrodes at a point spaced apart from a central portion of a capacitance formation region in a thickness direction by a distance equal to 25% of a thickness (S) of the capacitance formation region is T1, 0.8≦|T1 / Tc|≦1.0 is satisfied.

A multilayer ceramic electronic component includes: a ceramic main body; a plurality of internal electrodes laminated within the ceramic main body; and external electrodes formed on outer surfaces of the ceramic main body and electrically connected to the internal electrodes, wherein an average thickness of the external electrodes is 10 μm or less, and when a thickness of the external electrodes in a central portion of the ceramic main body in a width direction is Tc and a thickness of the external electrodes at a lateral edge of a printed surface region of the internal electrodes is T1, 0.5≦|T1 / Tc|≦1.0 is satisfied.

Disclosed is an improved method and system for implementing metal fill for an integrated circuit design. When an engineering change order is implemented, the existing dummy metal fill geometries are initially ignored when modifying the layout, even if this results in shorts and / or other DRC violations. Once the ECO changes have been implemented, those violations caused by interaction between the changes and the metal fill are repaired afterwards.

A high-efficiency semiconductor light emitting diode and a method for manufacturing the same are provided. The semiconductor LED has high internal quantum efficiency and can reduce the bad effect caused by the crystal defect. In the semiconductor light emitting diode, a conductive substrate has a three-dimensional top surface, and a light-emitting stack structure has a three-dimensional structure and includes an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer, which are sequentially formed on the conductive substrate. A p-electrode is formed on the p-type nitride semiconductor layer, and an n-electrode is formed on a bottom surface of the conductive substrate.

A vehicle brake apparatus capable of preventing abnormal vibration due to thickness variations in a disc rotor includes a motor drive unit configured to control the motor which presses the brake pad against the disc rotor, a brake pressure detection unit for detecting a braking pressure for pressing the brake pad, and a wheel speed sensor for detecting a rotation speed of the disc rotor. If an amount of variation in the detection values detected by the brake pressure detection unit during one rotation of the disc rotor exceeds a variation amount determination threshold value and a detection value variation frequency has a correlation with the rotation speed of the disc rotor and the detection value variation frequency exceeds a variation frequency determination threshold value, the motor drive unit controls the motor in inverted phase to the variation in the detection values.

Provided are a ceramic component and a method of manufacturing the ceramic component. The ceramic component includes a previously fired insulation ceramic base, a functional ceramic sheet bonded to the insulation ceramic base by a diffusion bonding layer having an anchoring structure, internal electrodes embedded into the functional ceramic sheet, and external electrodes connected to the internal electrodes. A functional ceramic paste corresponding to the functional ceramic sheet is applied to the insulation ceramic base and is dried to form a functional ceramic film. The functional ceramic film is pressed against the insulation ceramic base to anchor functional ceramic film into the insulation ceramic base for sure attachment. The functional ceramic film is fired to allow functional oxide materials included in the functional ceramic film to permeate the insulation ceramic base by solid diffusion to form the diffusion bonding layer and to change the functional ceramic film into the functional ceramic sheet.

A humidity sensor includes: a sensor chip including a capacitive humidity sensor element and a connection electrode, wherein the capacitive humidity sensor element includes a humidity sensitive film having relative permittivity changeable in accordance with humidity, and wherein the connection electrode is electrically connected to the humidity sensor element; a lead plate electrically connected to the connection electrode; and a mold for covering a connection portion between the connection electrode and the lead plate. The mold is disposed on the sensor chip and includes a groove. The humidity sensitive film is disposed in the groove. The humidity sensitive film has a height in the groove, the height equal to or lower than a surface of the mold. The height of the humidity sensitive film in the groove is homogeneous.

A method for manufacturing fuel cell bipolar plates involves heating and softening a nonwoven fabric including an electrically conductive powder and thermoplastic resin fibers of 0.1 to 20 μm diameter, and shaping the softened nonwoven fabric.

The present invention discloses a resonator gyroscope including an isolated resonator. One or more flexures support the isolated resonator and a baseplate is affixed to the resonator by the flexures. Drive and sense elements are affixed to the baseplate and used to excite the resonator and sense movement of the gyroscope. In addition, at least one secondary element (e.g., another electrode) is affixed to the baseplate and used for trimming isolation of the resonator. The resonator operates such that it transfers substantially no net momentum to the baseplate when the resonator is excited. Typically, the isolated resonator comprises a proof mass and a counterbalancing plate.

A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source / drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented.

The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.

A programmable resistance, chalcogenide, switching or phase-change material device includes a substrate with a plurality of stacked layers including a conducting bottom electrode layer, an insulative layer having an opening formed therein, an active material layer deposited over both the insulative layer, within the opening, and over selected portions of the bottom electrode, and a top electrode layer deposited over the active material layer. The device uses temperature and pressure control methods to increase surface mobility in an active material layer, thus providing complete coverage or fill of the openings in the insulative layer, selected exposed portions of the bottom electrode layer, and the insulative layer.

A contact for a semiconductor device is made by performing, inter alia, a CMP process on an interlayer insulation layer to expose a first hard mask layer of each conductive line. The interlayer insulation layer is partially removed. A second hard mask layer is formed on a resultant substrate. Another CMP process is performed on the second hard mask layer to expose the first hard mask layer of each conductive line. A hard mask pattern is formed by etching portions of the CMPed second hard mask layer. The interlayer insulation layer is etched by using the hard mask pattern as an etch barrier to open the contact forming regions of the substrate. A conductive layer is deposited on the resultant substrate to fill the opened contact forming regions. The conductive layer and the remaining hard mask pattern are removed to expose the first hard mask layer of each conductive line.

Disclosed is a method for manufacturing a soundproofing material by finely crushing a discarded car seat, mixing the crushed car seat with polyester fiber, low-melting polyester fiber such as LM PET, polypropylene fiber and hemp, and carding the resulting mixture, and a soundproofing material composition prepared thereby. The disclosed method allows recycling of polyurethane foam of the discarded car seat into a soundproofing material composition having superior appearance quality and soundproofing performance. The disclosed method also prevents generation of excessive static electricity and allows preparation of a soundproofing material with smooth surface.

The present invention relates to a susceptor for manufacturing an epitaxial wafer in which an epitaxial layer is grown through a reaction between a wafer and a source gas in a chamber, including a pocket where an opening portion is formed for the wafer to be arranged; a ledge portion where the wafer is supported; and a gas adjusting member that is positioned in an outer circumferential portion on an upper surface of the opening portion of the susceptor. The gas adjusting member has a first gas adjusting member that is formed in a predetermined area which faces a crystallization direction of the wafer <110>; a second gas adjusting member in a predetermined area that faces the crystallization direction of the wafer <110>; and a third gas adjusting member that is formed between the first gas adjusting member and the second gas adjusting member. The first gas adjusting member, the second gas adjusting member, and the third gas adjusting member are formed to have different sizes in the areas which are formed along the circumference of the wafer, and the first, second, and third gas adjusting members are formed to have different degrees of inclination from the central direction of the wafer toward the susceptor so as to change the gas flow. Accordingly, the different areas where the gas flow increasing and decreasing devices (gas adjusting members) are formed are formed in the outer circumferential portion of the susceptor, and thus a deviation in the thickness of the epi layer in a wafer edge portion can be decreased when the epitaxial layer is formed in the semiconductor wafer.