Edge etching apparatus for etching the edge of a silicon wafer

a silicon wafer and edge etching technology, which is applied in electrical apparatus, thin material processing, transportation and packaging, etc., can solve the problems of edge slippage, surface defects, and residual film deposits at the edge that may flake off, and achieve the effect of reducing the total thickness variation of the edge etching wafer

Inactive Publication Date: 2009-10-01
SUNEDISON SEMICON LIMITED UEN201334164H
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0014]In various other embodiments, the method further comprises reducing the total thickness variation of the edge-etched wafer to less than about 3 microns.

Problems solved by technology

Damaged edges may cause edge slip during thermal processing of the wafer.
In addition, rough or pitted edges may trap particles that can be later released in a wet cleaning bath.
If the edge is not sufficiently smooth, residual film deposits at the edge may flake off.
The flakes may come into contact with the surface of the wafer thereby causing surface defects.
While edge polishing has proven effective, this operation increases processing time and cost.
However, in these types of methods, it may be difficult to etch the peripheral edge of the wafer within the contour of a wafer notch.
One disadvantage of these types of edge etching operations is difficulty in separating the wafers after etching.
In fact, increased stock removal by double-sided polishing may increase the burden on the edge treatment (e.g., polishing) operation.

Method used

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  • Edge etching apparatus for etching the edge of a silicon wafer
  • Edge etching apparatus for etching the edge of a silicon wafer
  • Edge etching apparatus for etching the edge of a silicon wafer

Examples

Experimental program
Comparison scheme
Effect test

example 1

Evaluation of Edge Quality of Edge Etched Wafers

[0091]Edge portions of 15 P− 300 mm wafers were etched utilizing an edge etcher of the type shown in FIGS. 6-9. The edge portions were immersed in a pool of 300 ml of acidic etchant from the following mixture: 2.4 l of HNO3 (69 wt. %), 2 l of H3PO4 (85 wt %) and 0.55 l of HF (49 wt %).

[0092]Two runs were carried out, one in which an edge portion of 7 wafers were etched with the edge portion extended from the nearest peripheral edge point to a point approximately 8.5 mm from the nearest peripheral edge point. In the second run 8 wafers were etched with the edge portion extending to a point approximately 8.5 mm from the nearest peripheral edge point.

[0093]The etch time of the first, 7 wafer run was 300 seconds, with rotation reversal after 150 seconds. Silicon removal, based on OGP diameter (a comparison of wafer diameter prior to and after etching) was approximately 30 μm.

[0094]The etch time of the second, 8 wafer run was 360 seconds, w...

example 2

Determination of the Amount of Material Removed by Edge Etching

[0098]300 mm wafers (75) were cut from a single crystal silicon ingot. After edge grinding, the edge portions of the wafers were etched utilizing an edge etcher of the type shown in FIGS. 6-9.

[0099]The wafers were split into a first group of 39 wafers and a second group of 36 wafers. The first group of wafers was edge polished (EP-300-X, SpeedFam) for 11 seconds and the second group was edge polished for 8 seconds.

[0100]A third group (75) of wafers was cut from a single wafer and subjected to edge grinding and edge polishing (EP-300-X, SpeedFam). The edge polish was a conventional 13 seconds in length.

[0101]The edge etched wafers were then combined and double-sided polished. The wafers of the third group were also double-sided polished (AC-2000-P2, PeterWolters). The cassettes of all batches of wafers were combined and a finish polish was performed (LapMaster). The double-sided polish removed approximately 15 μm of mater...

example 3

Flatness Comparison between Wafers that were and were not Edge Polished

[0103]The flatness of the three batches of wafers of Example 2 was determined by both GBIR, SBIR and SFQR methods after finish polishing. The results are shown in Table 1 below.

TABLE 1Flatness data for edge etched wafers and non-edge etchedwafers after double-sided polishing and finish polishingAverageAverageAverage SBIR MaxSFQR MaxNon-Edge Etched (13 sec)308.7118.729.8Edge Etched (11 sec)315.9124.541.3Edge Etched (8 sec)299.8108.537.0

As can be seen from Table 1, edge etching did not significantly degrade the flatness of finish polished wafers.

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Abstract

The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims the benefit of U.S. Provisional Application No. 61 / 040,857, filed Mar. 31, 2008.FIELD OF THE DISCLOSURE[0002]The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to apparatus and methods for etching the edge of a silicon wafer.BACKGROUND OF THE DISCLOSURE[0003]Semiconductor wafers are generally prepared from a single crystal ingot (e.g., a silicon ingot) which is trimmed and ground to have one or more flats or notches for proper orientation of the wafer in subsequent procedures. The ingot is then sliced into individual wafers. The individual wafers are subjected to a number of processing operations to reduce the thickness of the wafer, remove damage caused by the slicing and / or other processing operations, and to create at least one highly reflective surface (e.g., on a front surface of the wafer).[0004]In addition to having at least one highly reflective surface, semi...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): C23F1/08
CPCH01L21/02019H01L21/02021H01L21/30608H01L21/67086H01L21/67313Y10T428/21Y10T428/219
Inventor ERK, HENRY F.ALBRECHT, PETER D.HOLLANDER, EUGENE R.DOANE, THOMAS E.SCHMIDT, JUDITH A.VANDAMME, ROLANDZHANG, GUOQIANG (DAVID)
Owner SUNEDISON SEMICON LIMITED UEN201334164H
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