A Bit Synchronization Circuit Used in Zero-IF GFSK Demodulator

Abstract

The invention proposes a bit synchronization circuit for a zero-intermediate-frequency GFSK demodulator. A shift register module is used to store a sampling value; a correlation value calculation module is used to calculate the correlation values of two signals; a correlation value accumulation module is used to calculate the sum of the correlation values; a comparator module is used to obtain a bit synchronization signal pulse; and finally, a delayer module is used to delay the pulse by a period of time to obtain a final correct bit synchronization signal. The bit synchronization circuit is applicable to a GFSK modulation signal of a lead code in which 0101 appears alternately, and the modulation coefficient is large. The theoretical basis is that the GFSK modulation signal of the lead code in which 0101 appears alternately is of bilateral symmetry, and the axis of symmetry is just the code element end moment. The bit synchronization circuit has the advantages of simple structure and accurate synchronization.

Description

technical field [0001] The invention relates to the technical field of wireless communication bit synchronization, in particular to a bit synchronization circuit used in a zero-IF GFSK demodulator. Background technique [0002] Wireless communication systems play an important role in modern life. Gauss Frequency Shift Keying (GFSK for short) has been widely used in transceivers of short-distance wireless communication protocols. The GFSK demodulator is an important part of the receiver, and its performance has a great influence on the performance of the receiver. The zero-IF GFSK demodulator has the advantages of simple implementation and low power consumption. The bit synchronization circuit plays a key role in the zero-IF GFSK demodulator. [0003] Based on the fact that the end of the symbol is most likely to be between the sampling moments of the change in the direction of the phase rotation, the literature Lee E K B, Powell C C, Kwon H M.A novel wireless communicatio...

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Problems solved by technology

[0003] Based on the fact that the end of the symbol is most likely to be between the sampling moments of the change in the direction of the phase rotation, the literature Lee E K B, Powell C C, Kwon H M.A novel wireless communication device and its synchronization scheme[C] / / Global Telecommunications Conference, 1995.GLOBECOM '95.,IEEE.IEEE,1995,1:659-663. Utilize the index value of four or more zero-crossing points to estimate the symbol end time, this estimation function needs to use the multiplier of 2 multi-bit widths and A divider with a multi-bit width has the disadvantages of occupying more resources, complex structure, and low synchronization accuracy

At the same time, this document also proposes an improved bit synchronization algorithm with high synchronization accuracy, but does not give a specific circuit structure, and it can be predicted that this improved bit synchronization algorithm will consume huge hardware resources

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