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A method for forming a through-silicon via interconnection structure

An interconnection structure and through-silicon via technology, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, and circuits, can solve problems such as leakage, cracking of the passivation layer 21, and cracking of the passivation layer, so as to solve leakage current and improve Reliability, easy-to-achieve results

Active Publication Date: 2017-11-28
JIANGYIN CHANGDIAN ADVANCED PACKAGING CO LTD
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  • Summary
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this method has problems such as the breakage of the passivation layer 21 caused by the mechanical polishing method, the protrusion of the surface of the metal pillar 3 caused by the polishing process, and the insertion of metal ions into the passivation layer 21 caused by polishing to form leakage, such as Figure 1, the above problems generally occur when the metal pillar 3 is exposed The opening area or the area adjacent to the opening, such as the I area marked in the figure
The reason why the above-mentioned Cureveal process adopts such a complex process is to overcome the cracking of the passivation layer caused by the chemical-mechanical polishing method, the protrusion of the metal surface caused by the polishing process, and the embedding of metal ions into the passivation layer caused by polishing. Leakage and other problems
However, the Cu reveal process is not only complicated, but also has the phenomenon that the exposed height of the metal in the TSV is uneven relative to the silicon substrate after silicon etching, which directly affects the subsequent metal exposure yield and the progress of the photolithography process.

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  • A method for forming a through-silicon via interconnection structure
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  • A method for forming a through-silicon via interconnection structure

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Embodiment Construction

[0037] see figure 2 , a method for forming a through-silicon via interconnection structure of the present invention includes:

[0038] Executing step S101, providing a silicon substrate with a through-silicon via structure, above which is a semiconductor process layer;

[0039] Execute step S102, thinning the thickness under the silicon substrate by mechanical grinding to expose the lower surface of the metal pillar;

[0040] Execute step S103, and form a metal block on the lower surface of the metal pillar by sputtering the metal seed layer, photolithography, and electroplating in sequence;

[0041] Executing step S104, further thinning the thickness under the silicon substrate by wet etching to expose the lower end of the metal pillar;

[0042] Execute step S105, depositing a passivation layer II on the lower surface of the silicon substrate to cover the lower surface of the silicon substrate and the metal block, and opening an opening for the metal block;

[0043] Execu...

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Abstract

The invention relates to a silicon through hole interconnection structure forming method, which belongs to the technical field of semiconductor packaging. The method comprises steps: a silicon substrate with a silicon through hole structure is provided; a mechanical polishing method is used for thinning the silicon substrate until the lower surface of a metal column is exposed; a metal block is formed on the lower surface of the metal column; the lower thickness of the silicon substrate is further thinner in a wet etching method, and the lower end of the metal column is exposed; a passivation layer II is deposited on the lower surface of the silicon substrate for covering the lower surface of the silicon substrate and the metal block, and the metal block is provided with an opening; a re-wiring metal layer is selectively formed on the surface of the passivation layer II, and one end of the re-wiring metal layer extends to the metal block via the opening of the metal block and is fixedly connected with the metal block; and a protection layer coats the re-wiring metal layer. Through thinning the silicon substrate to enable a defect region I to be exposed and using the passivation layer to fill the defect region, the problem of leakage current is solved, reliability of the silicon through hole interconnection structure is improved, and the method of the invention has better control performance.

Description

technical field [0001] The invention relates to a method for forming a through-silicon hole interconnection structure, which belongs to the technical field of semiconductor packaging. Background technique [0002] In the advanced packaging technology characterized by through silicon vias (Through silicon vias), one of the biggest difficulties is the exposure of the metal pillars 3 in the through silicon vias 12 . Generally, the exposure of the metal in the TSV 12 is performed by chemical-mechanical polishing. However, this method has problems such as the breakage of the passivation layer 21 caused by the mechanical polishing method, the protrusion of the surface of the metal pillar 3 caused by the polishing process, and the embedding of metal ions into the passivation layer 21 caused by polishing to form leakage, such as figure 1 As shown, the above-mentioned problems generally occur in the exposed opening area of ​​the metal pillar 3 or the area adjacent to the opening, su...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/302H01L21/31
CPCH01L21/30625H01L21/31H01L21/76897
Inventor 张黎龙欣江赖志明陈栋陈锦辉
Owner JIANGYIN CHANGDIAN ADVANCED PACKAGING CO LTD