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Device and method for correcting error estimation of analog-digital converter

一种模数转换器、误差估计的技术，应用在模数转换器、模/数转换、模拟/数字转换校准/测试等方向，能够解决估计校正收敛速度慢、增加单次估计所需的时间等问题，达到减少采样的样本点数、降低持续时间的要求、缩减校正收敛速度的效果

Active Publication Date: 2015-10-21
NO 24 RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide an analog-to-digital converter error estimation and correction device and method thereof, which are used to solve the problem in the prior art when using samples When there are many points, the time required for a single estimation is increased, which leads to the problem of slow convergence of estimation correction

Method used

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  • Device and method for correcting error estimation of analog-digital converter
  • Device and method for correcting error estimation of analog-digital converter
  • Device and method for correcting error estimation of analog-digital converter

Examples

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Embodiment 1

[0075] In the correction of the dual-channel time division multiplexing analog-to-digital converter (TI ADC), the clock signal generator of the TI ADC generates a first clock signal and a second clock signal according to the clock signal; the first clock signal and the The second clock signal is a clock signal with the same period and a phase difference of 180 degrees, and the first channel sub-ADC samples and holds the input signal on the period of the first clock signal to provide the first channel The digital signal is a reference signal; the second channel sub-ADC samples and holds the input signal on the period of the two clock signals, so as to provide the second digital signal as a signal to be corrected.

[0076]And a digital control analog delay cell 10 (digital control delay cell, DCDC) is set in the sampling clock path of the second digital signal, which can fine-tune the clock phase so as to correct the second clock signal relative to the first clock signal. phase ...

Embodiment 2

[0097] Take the single-channel 250MHz, dual-channel time-interleaved 500MHz sampling rate 14-bit A / D converter as an example for specific description. When the two channel sub-ADCs sample the input signal in parallel, between the sampling clocks, the phase difference between the first clock signal and the second clock signal is 180 degrees, and the sampling period is 4 ns. Set the reference channel ADC output data to y 1 (n); Correction channel ADC output data is y 2 (n). DCDC is a digitally controlled analog delay unit 10, controlled by 8-bit binary codes (0-255), with a total of 256 codes, and the delay step adjusted corresponding to the unit code is 60 fs. Insert the same DCDC in the ADC clock path of the reference channel as that in the ADC clock path of the correction channel; the control code of the DCDC in the ADC clock path of the reference channel is fixed at 128, and the fixed delay is 7.68ps; the ADC clock path of the correction channel The DCDC control code is d...

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Abstract

The invention provides a device and a method for correcting error estimation of an analog-digital converter. The method comprises the steps as follows: generating a control signal to finely adjust a numerical control simulation time delay unit according to a correction parameter initial value which is set in advance to adjust time delay amount and correct clock phase error among channels; correcting gain error among channels according to the correction parameter initial value and generating a totality correction signal, buffering the totality correction signal and triggering a counting unit to count, simultaneously calling the totality correction signal in a cache and generating an initial estimation result by using a circular correlation method; setting enabling ends of a low pass filter accumulation unit and a correction parameter updating unit while counting to a preset value, generating the error estimation with the initial estimation result and latching, updating a clock correction parameter and a gain correction parameter according to a gradient descent method, and latching the clock correction parameter and the gain correction parameter, and resetting to correct circulation estimation. The device and the method of the invention improve the estimated accuracy and quickens convergence rate of the estimation correction under the condition of using few effective sample points.

Description

technical field [0001] The invention belongs to the technical field of Analog-to-Digital Converter (ADC), and more particularly relates to a device and method for estimating and correcting gain and clock phase errors of a dual-channel time-division multiplexing converter. Background technique [0002] In recent years, time-interleaved analog-to-digital converters (TI ADCs) have become increasingly available in applications that require extremely high sampling rates and sampling accuracy (i.e., cannot be achieved by a single ADC today). attention. In a TI ADC using M channel sub-ADCs, each channel sub-ADC operates at Fs / M, where Fs is the sampling rate of the TI ADC. The outputs from each channel sub-ADC are combined at Fs using a multiplexer (MUX) to produce a sample rate converter operating at Fs. However, due to factors such as process errors, temperature, voltage, and environmental disturbances, there are gain and clock phase errors between channels and will change with...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10H03M1/12
CPCH03M1/1028H03M1/1215H03M1/0609H03M1/10
Inventor 蒲杰胡刚毅沈晓峰徐学良付东兵张瑞涛王友华王育新陈光炳李儒章
Owner NO 24 RES INST OF CETC
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