Delay-locked loop adopting novel error lock detection circuit

Abstract

The invention discloses a delay-locked loop adopting a novel error lock detection circuit, comprising the error lock detection circuit, a phase detector, a charge pump, a low pass filter and a voltage control delay line. The error lock detection circuit detects all output phase clocks of the voltage control delay line, inputs a detection signal into the phase detector, and outputs a charge-discharge control signal to the charge pump. Through adoption of the delay-locked loop, the problem of harmonic wave locking of the conventional delay-locked loop in a broadband range is solved, the harmonic wave locking is eliminated, and a multiphase output of fixed time delay is provided.

Description

technical field [0001] The invention relates to a clock signal generation circuit, in particular to a delay-locked loop adopting a novel error lock detection circuit. Background technique [0002] With the continuous increase of the amount of data processed by integrated circuit chips per unit time, the speed of signal processing inside the chip is required to increase accordingly, that is, the clock frequency needs to be continuously increased. Therefore, as the key core module clock circuit in digital integrated circuit chips, its own Performance indicators directly affect the realization of overall chip performance. In order to meet the needs of users for the diversification of chip functions, more and more module circuits are integrated on the same chip for the sake of cost reduction. Due to the limitation of PCB cost and technology, it is difficult for the off-chip clock to generate the required higher frequency clock for the chip, so it is inevitable to design the clo...

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Problems solved by technology

[0005] Purpose of the invention: In order to overcome the deficiencies in the prior art, the present invention provides a delay-locked loop using a new type of error-l

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