A method for improving line width roughness of gate structure

Abstract

The present invention provides a method for improving the line width roughness of a gate structure, comprising: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate, and forming a first isolation layer on a side wall of the gate structure; Form a second isolation layer on the top of the gate structure, the top and sidewalls of the first isolation layer, and the semiconductor substrate; form a sacrificial material layer on the second isolation layer; etch back the sacrificial material layer to expose the second isolation layer located on the top of the gate structure and the top of the first isolation layer; etching and removing the second isolation layer located on the top of the gate structure and the top of the first isolation layer; removing the remaining sacrificial material layer; removing the first isolation layer; annealing in hydrogen atmosphere; removing the second isolation layer. According to the present invention, the line width roughness of the gate structure is effectively controlled within a certain range by performing annealing treatment in a hydrogen atmosphere, thereby improving the overall performance of the device.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for improving the line width roughness of a gate structure. Background technique [0002] When the critical dimension of semiconductor devices drops below 100nm, the impact of Line Width Roughness (LWR) on integrated circuit processing technology can no longer be ignored, and it has become one of the bottleneck factors that seriously restrict the sustainable development of integrated circuits and related industries. In particular, the line width roughness of the gate can lead to problems of Vt mismatch and high LOFF. Therefore, it is necessary to control the line width roughness of the gate within the range of 8% of the total critical dimension. The current methods to improve the line width roughness of the gate structure focus on the H 2 / HBr pre-treatment or process adjustment, but this still cannot meet the needs. [0003] Thermal annealing in a hydrogen atmo...

AI Technical Summary

Problems solved by technology

In particular, the line width roughness of the gate can lead to problems of Vt mismatch and high LOFF, so it is necessary to control the line width roughness of the gate within the range of 8% of the total critical dimension

The current methods to improve the line width roughness of the gate structure focus on the H 2 / HBr pre-treatment or process adjustment, but this still cannot meet the needs

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