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Systems and methods for encoding and decoding of check-irregular non-systematic ira codes

An irregular and non-systematic technology, applied in the field of systems and methods for encoding and decoding irregular non-systematic IRA codes, can solve problems such as non-convergence, and achieve the effect of improving the convergence rate of decoding

Inactive Publication Date: 2015-12-02
LN2 DB LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, experimental simulation results show that check rule non-systematic IRA codes such as that from Park et al. do not converge in many cases

Method used

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  • Systems and methods for encoding and decoding of check-irregular non-systematic ira codes
  • Systems and methods for encoding and decoding of check-irregular non-systematic ira codes
  • Systems and methods for encoding and decoding of check-irregular non-systematic ira codes

Examples

Experimental program
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Embodiment Construction

[0041] Check irregular non-systematic IRA encoders and transmitters

[0042] According to some implementations in figure 1 A typical simplified transmitter with a check-irregular non-systematic IRA encoder is shown in . Transmitter 5100 includes a set of bit repeaters of different degrees, also referred to as bit repeater nodes, collectively referred to as irregular bit repeaters 5101, wherein irregular bit repeaters 5101 combine the information on line 5107 in an irregular form The bit sequence u repeats. For example, a bit repeater of degree m produces m identical copies of an information bit, as is known in the art. These repeated information bits represent the first level coded bits. The interleaver 5102 performs a pseudo-random permutation on the repeated sequence of bits v on line 5108 and produces interleaved first-level coded bits v' on line 5109 .

[0043] A set of check node combiners of different degrees, collectively referred to as check nodes 5103, operates on...

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Abstract

Systems and methods for encoding and decoding check-irregular non-systematic IRA codes of messages in any communication or electronic system where capacity achieving coding is desired. According to these systems and methods, IRA coding strategies, including ones that employ capacity-approaching non-systematic IRA codes that are irregular and that exhibit a low error floor, are employed. These non-systematic IRA codes are particularly advantageous in scenarios in which up to half of coded bits could be lost due to channel impairments and / or where complementary coded bits are desired to transmit over two or more communications sub-channels. An encoder includes information bit repeaters and encoders, one or more interleavers, check node combiners, a check node by-pass and an accumulator. A decoder includes a demapper, one or more check node processors, an accumulator decoder, a bit decoder, and one or more interleavers / deinterleavers.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to U.S. Patent Application Serial No. 13 / 693,029, entitled "System and Method for Encoding and Decoding Check Irregular Non-Systematic IRA Codes," filed December 3, 2012 by the same inventors rights, the entire contents of which are incorporated herein by reference. technical field [0003] The present invention relates to methods and systems for encoding and decoding messages in any communication system in which it is desired to achieve encoded capacity, including all digital or hybrid digital radio (HD radio or HDR) communication transmitters and receivers , and other wireless or wired communication systems. Background technique [0004] Turbo codes and Low Density Parity Check (LDPC) codes are advanced forward error correction (FEC) schemes. These codes are known to approach the Shannon limit in performance as the block size increases. Likewise, these codes are used in the design ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/00
CPCH03M13/1197H03M13/09H03M13/098H03M13/152H03M13/255H03M13/2906H03M13/611H03M13/6362H04L1/0041H03M13/1111H03M13/296H03M13/356H03M13/3746H03M13/3761
Inventor 布拉尼米尔·R·沃伊契奇斯蒂利亚诺斯·帕帕哈拉拉伯斯
Owner LN2 DB LLC
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