Error correction method used for NAND-FLASH-adopted electric power acquisition terminal

Abstract

The invention discloses an error correction method used for a NAND-FLASH-adopted electric power acquisition terminal, which comprises the following steps: determining to adopt a BCH (Bose, Ray-Chaudhuri and Hocquenghem) CODE algorithm to realize data error correction; in the BCH CODE algorithm, determining that a minimum error correction unit fixedly has 512 bytes and 4 error correction bits; according to a rule that the minimum error correction unit fixedly has 512 bytes and 4 error correction bits, generating an index table used for error correction bit flipping; storing the index table in a memory area ROM (Read Only Memory) of codes required by the electric power acquisition terminal; carrying out a data reading operation on Nand Flash by an application program on the electric power acquisition terminal, and utilizing the index table stored in the memory area in the step 4) by the CODE algorithm to realize data correction through a BCH algorithm if 1 or 2 or 3 or 4-bit bit flipping is in the presence. The error correction method has the advantages that a backup power supply can be called to realize a purpose that a lamp of a bathroom can normally illuminate after outage.

Description

technical field [0001] The invention relates to an error correction method for a power collection terminal using NAND FLASH. Background technique [0002] At present, power collection terminals on the market usually use NANDFLASH as a storage device. There are two architectures for NANDFLASH, namely SLC architecture and MLC architecture. The SLC architecture is characterized by high cost, small capacity, and fast read and write speed; the MLC architecture is characterized by Large capacity and low cost, but the reading and writing speed is relatively slow. Due to process problems, the minimum writing unit (usually 512 bytes) of this type of memory will produce one or more bit displacements. Among them, the SLC process The capacity is relatively small, usually 512 bytes will only produce 1 bit flip; the MLC process has a large capacity, usually 512 bytes are prone to 4 bit flips. Most of the existing power collection terminals on the market use 1Gbit SLC-based NANDFLASH. Rel...

AI Technical Summary

Problems solved by technology

The power collection terminal needs to be upgraded to 2Gbit NAND FLASH. If it is upgraded to 2Gbit NAND FLASH, it will bring the following technical difficulties and risks: to upgrade to 2Gbit NAND FLASH, it is necessary to use a 4-bit error correction algorithm (for 4-bit flip phenomenon), of which 4-bit error correction algorithm, generally The BCH error correction algorithm is used, but because the BCH error correction algorithm is dynamically running, the number of bytes in the error correction basic unit and the number of error correction bits are determined by the input parameters. The number of error correction bits can be 4 bits, 8 bits, and 16 bits respectively. 4 bits, the number of error correction bits is 4 bits, which means that it can correct 1, 2, 3, and 4 bit flips. Since the parameters are variable, building an index table will take up a lot of memory. For 512 bytes of 4-bit error correction At least 70k RAM is required, and the cost of running on an embedded platform with a small memory is too high. However, existing power collection terminals have large memory (arm+linnux platform, external expansion of tens of megabytes of memory), small memory (cortexM3 / M4 platform, No external RAM) two

The above-mentioned error correction algorithm cannot run on a small memory platform or a platform without external memory expansion

Its memory capacity must be increased to run the BCH error correction algorithm and finally be upgraded to 2GbitMLCNANDFLASH, but this will increase the production cost of the power collection terminal

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