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On-chip lead-out structure and manufacturing method of a chip

A technology for extracting structures and chips, which is applied in semiconductor devices, semiconductor/solid-state device components, electrical components, etc., and can solve problems such as virtual soldering, decreased bonding force between metal thin film and substrate, and peeling off

Active Publication Date: 2019-03-08
SUZHOU GANXIN MICRO SYST TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, although these methods may temporarily realize the electrical connection between the wire and the device, due to the small soldering contact area, the solder is very easy to degrade and soften after being used at high temperature for a period of time; or the soldering point is stressed due to bending and other actions, thus appearing The bonding force between the metal film on the chip and the substrate decreases, falls off, and there is a virtual soldering

Method used

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  • On-chip lead-out structure and manufacturing method of a chip
  • On-chip lead-out structure and manufacturing method of a chip
  • On-chip lead-out structure and manufacturing method of a chip

Examples

Experimental program
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Effect test

Embodiment 1

[0029] On the front side of the silicon wafer, use wet anisotropic etching, such as KOH to etch a V-shaped groove, and then use sputtering or evaporation to form a uniform 0.1-3 micron thick metal film in the groove to ensure that the side wall of the groove It is completely covered by a metal film, and a V-shaped groove pattern is etched out by a photolithography process as an interface for electrical connection.

[0030] When welding, insert metal wire or multi-strand metal wire strands with a diameter not larger than the width of the V-shaped groove into the above-mentioned V-shaped groove, and use manual welding to fill the entire groove with solder to form a firm welding structure. So far, the direct lead of the metal wire on the chip is directly drawn out.

[0031] When the wire is subjected to external force, since the surface area of ​​the metal wire in the V-shaped groove is larger than that of the plane welding, the probability of false welding of the wire is much sm...

Embodiment 2

[0033] On the front side of the silicon wafer, use wet anisotropic etching, such as KOH to etch a trapezoidal groove, and then use dry etching, such as DRIE, to etch a circle with a diameter not smaller than the diameter of the wire at the other end of the groove away from the lead-out end. hole. According to actual needs, use sputtering or evaporation process to form a layer of metal film on the back of the chip, or in the groove on the front of the chip, or on the front and back of the chip, to ensure that the side wall of the groove is completely covered by the metal film, and the electrode pattern is etched by photolithography. Interface for electrical connection.

[0034] When welding, first pass the metal wire or multi-strand metal wire stranded wire with a diameter not larger than the width of the V-shaped groove into the hole from the front, and leave a small section on the back, and then bend the wire to make it follow the direction of the trapezoidal groove Extend, ...

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Abstract

The invention relates to an on-chip wire direct lead-out structure of a chip and a making method thereof, and belongs to the field of electronic devices. The making method is characterized by comprising the following steps: using a micro machining method to form a wire accommodating slot on the surface of a silicon wafer, wherein the slot is V-shaped, trapezoidal, U-shaped, arc or square or the slot is a combined groove, pit or through hole; and then, making a metal electrode on the slot, thus obtaining a direct lead-out structure for wires from hundred microns to millimeter level. A direct lead-out structure for wires from hundred microns to millimeter level realized on a chip is provided. Therefore, the connection strength of a wire and a chip is improved significantly, and the problem of circuit breaking caused by damage to the connection of a wire and a chip due to the change in the external environment such as temperature or pressure and personnel operation is avoided.

Description

technical field [0001] The invention relates to a direct lead-out structure and a manufacturing method of an on-chip wire on a chip, belonging to the category of electronic devices. Background technique [0002] In the process of IC chip or MEMS chip packaging, in order to maintain a certain degree of flexibility or freedom of the product, or to meet the application requirements at a specific volume and temperature, sometimes it is not possible to use a tube or plastic package for electrical connection, only Use wire leads directly on the chip to realize electrical signal collection or power supply to the chip. In this way, in the process of packaging or post-packaging operation and use, due to factors such as high temperature and vibration, the joint between the wire and the chip will often be subjected to huge stress. Since the diameter of the wire is thicker than that of the chip, and the surface of the chip is smoother, heat welding, laser welding and other methods are ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/49H01L23/482
CPCH01L24/42H01L24/85
Inventor 李铁周宏王翊
Owner SUZHOU GANXIN MICRO SYST TECH
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