Chip packaging structure and method
A chip packaging structure and chip packaging technology, applied in electrical components, electrical solid devices, circuits, etc., can solve the problems of light waste, side light leakage of packaged finished products, low production efficiency, etc., to increase mechanical strength, simplify packaging process, improve The effect of production efficiency
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[0047] In order to make the present invention more comprehensible, the specific implementation manners of the present invention will be described in detail below in conjunction with the accompanying drawings. For convenience of description, the components in the structures in the drawings of the embodiments are not scaled according to the normal scale, so they do not represent the actual relative sizes of the structures in the embodiments. The above or upper side of the structure or surface includes the case where there are other layers in the middle.
[0048] Such as Figure 1a-Figure 1k Shown, a kind of chip packaging method comprises the following steps:
[0049] A. see Figure 1a with Figure 1b , providing a first substrate, the first substrate has a plurality of first substrate units 1 corresponding to a plurality of chips to be packaged, the first substrate unit has a first surface 101 and an opposite second surface 102, in the first The second surface 102 of the su...
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