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Wafer cutting method

A cutting method and wafer technology, which can be used in electrical components, fine working devices, semiconductor/solid-state device manufacturing, etc., can solve problems such as chipping at the top edge of deep reactive ion etching trenches

Inactive Publication Date: 2016-03-30
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

[0003] At present, in the dicing process of deep reactive ion etching (DRIE), the DRIE step is first performed on the front side of the wafer to form deep trenches, and then the back grinding (Grinding) to deep reactive ion etching trenches (DRIEtrench) , exposing the groove to achieve the purpose of cutting (Dicing), such as figure 1 However, the cutting and pressure of the grinding wheel on the wafer during the grinding (Grinding) process can easily lead to severe chipping at the top edge of the deep reactive ion etching trench, such as figure 2 shown

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Embodiment 1

[0043] Current methods for dicing wafers with high-aspect-ratio trenches are figure 1 As shown, a semiconductor substrate 102 is firstly provided, and several trenches 103 with a high aspect ratio are formed in the semiconductor substrate 102 by means of deep reactive ion etching (DRIE), and then the front surface of the semiconductor substrate is bonded. Put a layer of tape (tape) 101 on it, and reverse the semiconductor substrate 102 for back grinding, so as to expose the trench 103 with high aspect ratio, so as to achieve the purpose of cutting (Dicing), such as figure 1 shown.

[0044] In DRIE cutting, the cutting and pressure of the grinding wheel on the wafer when approaching the groove 103 and the grinding trench (grinding trench) can easily cause severe chipping (chipping) on ​​the top of the groove 103, such as figure 2 shown.

[0045] In order to solve the problems existing in the prior art, the present invention provides a new wafer cutting method, the following ...

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Abstract

The invention relates to a wafer cutting method, and the method comprises the steps: A1, providing a wafer, and forming a trench in the wafer; A2, filling the trench with a temporarily selected material, so as to support the trench; A3, grinding of the back surface of the wafer, so as to expose the temporarily selected material; A4, removing the temporarily selected material, and exposing the trench, so as to complete the cutting of the wafer. In order to solve a problem that the grinding in the DRIE cutting technology causes the crack of the contour of the trench, the invention provides the new DRIE cutting method. In the method, the cavity of the trench is filled through temporary bonding glue after DRIE, the bonding glue is solidified through soft bake, and the back grinding is carried out, thereby enabling the edge of the wafer to be supported in a grinding process and not to be cracked. After grinding, a corresponding solvent is used for removing the temporary bonding glue, thereby solving a crack problem and improving the cutting efficiency and yield.

Description

technical field [0001] The present invention relates to the field of semiconductors, in particular, the present invention relates to a wafer cutting method. Background technique [0002] In the manufacturing process of semiconductor devices, after circuits are formed in the wafer, the wafer needs to be diced. The dicing is a process of dividing the wafer into chips or grain units with complete circuit systems. [0003] At present, in the dicing process of deep reactive ion etching (DRIE), the DRIE step is first performed on the front side of the wafer to form deep trenches, and then the back grinding (Grinding) to deep reactive ion etching trenches (DRIEtrench) , exposing the groove to achieve the purpose of cutting (Dicing), such as figure 1 However, the cutting and pressure of the grinding wheel on the wafer during the grinding (Grinding) process can easily lead to severe chipping at the top edge of the deep reactive ion etching trench, such as figure 2 shown. [0004]...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/78B28D5/00
Inventor 施林波陈福成
Owner SEMICON MFG INT (SHANGHAI) CORP
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