High-K metal gate CMOS device and forming method thereof

A metal gate and device technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problem of no barrier layer, affecting the work function value of the PMOS work function metal layer 15, and the small size of the second gate opening 112 and other issues to achieve the effect of eliminating the impact

Inactive Publication Date: 2016-03-30
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

As mentioned above, Al begins to diffuse above 350°C, and many process steps in the current back-end process (BEOL) exceed 350°C, therefore, Al will inevitably diffuse to the underlying PMOS work function metal layer 15 , thereby affecting the work function value of the PMOS work function metal layer 15
[0014] In order to prevent Al from diffusing into the PMOS

Method used

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  • High-K metal gate CMOS device and forming method thereof
  • High-K metal gate CMOS device and forming method thereof
  • High-K metal gate CMOS device and forming method thereof

Examples

Experimental program
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Example

[0065] First instance

[0066] reference Figure 7 , A semiconductor substrate 20 is provided. The semiconductor substrate 20 includes a parallel NMOS region and a PMOS region. The semiconductor substrate 20 may be, for example, a silicon substrate or other suitable substrates used in semiconductor processing. An isolation structure 201 may be formed in the semiconductor substrate 20, such as a shallow trench isolation structure (STI).

[0067] A dielectric layer 21 is formed on the semiconductor substrate 20. The dielectric layer 21 has a first gate opening 211 in the NMOS region and a second gate opening 212 in the PMOS region. Sidewall spacers 213 may be formed in the dielectric layer 11 around the first gate opening 211 and the second gate opening 212. An active region 214 and a drain region 215 can be formed in the semiconductor substrate 10 on both sides of the first gate opening 211 and the second gate opening 212.

[0068] The following briefly introduces the formation pro...

Example

[0085] Second instance

[0086] The steps of the second example are the same as those of the aforementioned first example Figure 7 to Figure 11 The steps shown are all the same, the difference is that the process after the formation of the PMOS work function metal layer 28 is slightly different.

[0087] reference Figure 13 , At the first thickness of the PMOS work function metal layer 28 (see Picture 12 ) After the formation, the same material can be deposited to increase the thickness, that is, the PMOS work function metal layer 28' with the preset second thickness is formed. As the thickness of the PMOS work function metal layer 28' increases, its equivalent work function value also increases. In addition, the thicker PMOS work function metal layer 28' also helps prevent Al diffusion into the PMOS work function metal layer 28'.

[0088] Then, the metal material 30 is filled in the first gate opening and the second gate opening to form a gate electrode. The formation process ...

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Abstract

The invention provides a high-K metal gate CMOS device and a forming method thereof. The method includes the steps of: providing a semiconductor substrate including an NMOS region and a PMOS region, wherein the semiconductor is covered by a dielectric layer, and the dielectric layer has a first gate opening and a second gate opening in the NMOS region and PMOS region respectively; sequentially depositing a high-K material layer, a first cap layer, a barrier layer and an NMOS work function metal layer; performing imaging on the NMOS work function metal layer, the NMOS work function metal layer located at the bottom of the first gate opening and a side wall adjacent to the bottom being kept, and the rest of the NMOS work function metal layer being removed; and depositing a PMOS work function metal layer having a first thickness, the PMOS work function layer covering the barrier layer and bottoms and side walls of the first gate opening and the second gate opening. The method provided by the invention can eliminate influence of Al diffusion on the PMOS work function metal layer, and additional arrangement of a barrier layer is not needed.

Description

technical field [0001] The invention relates to a high-K metal gate CMOS technology, in particular to a high-K metal gate CMOS device and a forming method thereof. Background technique [0002] The technology of combining metal gates with high-K dielectric materials is considered to be a promising technology, especially for CMOS processes below 45nm. The equivalent work function required by the metal gate of a CMOS field effect transistor should be close to that of a traditional highly doped polysilicon gate, usually 4.1eV to 4.3eV for an N-type field effect transistor, and for a P-type field effect transistor For transistors, it is usually 4.7eV to 4.9eV. Therefore, finding an appropriate work function is very important for the high-K metal gate process (HKMG). [0003] Currently, TiAl (with a work function of ~4.2eV) and TiN (with a work function of ~4.8eV) are currently very popular in high-K metal gate processes because their work function values ​​for NMOS transistors...

Claims

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Application Information

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IPC IPC(8): H01L21/8238H01L21/28H01L27/092H01L29/49
Inventor 库尔班·阿吾提
Owner SEMICON MFG INT (SHANGHAI) CORP
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