High-K metal gate CMOS device and forming method thereof

Abstract

The invention provides a high-K metal gate CMOS device and a forming method thereof. The method includes the steps of: providing a semiconductor substrate including an NMOS region and a PMOS region, wherein the semiconductor is covered by a dielectric layer, and the dielectric layer has a first gate opening and a second gate opening in the NMOS region and PMOS region respectively; sequentially depositing a high-K material layer, a first cap layer, a barrier layer and an NMOS work function metal layer; performing imaging on the NMOS work function metal layer, the NMOS work function metal layer located at the bottom of the first gate opening and a side wall adjacent to the bottom being kept, and the rest of the NMOS work function metal layer being removed; and depositing a PMOS work function metal layer having a first thickness, the PMOS work function layer covering the barrier layer and bottoms and side walls of the first gate opening and the second gate opening. The method provided by the invention can eliminate influence of Al diffusion on the PMOS work function metal layer, and additional arrangement of a barrier layer is not needed.

Description

technical field [0001] The invention relates to a high-K metal gate CMOS technology, in particular to a high-K metal gate CMOS device and a forming method thereof. Background technique [0002] The technology of combining metal gates with high-K dielectric materials is considered to be a promising technology, especially for CMOS processes below 45nm. The equivalent work function required by the metal gate of a CMOS field effect transistor should be close to that of a traditional highly doped polysilicon gate, usually 4.1eV to 4.3eV for an N-type field effect transistor, and for a P-type field effect transistor For transistors, it is usually 4.7eV to 4.9eV. Therefore, finding an appropriate work function is very important for the high-K metal gate process (HKMG). [0003] Currently, TiAl (with a work function of ~4.2eV) and TiN (with a work function of ~4.8eV) are currently very popular in high-K metal gate processes because their work function values ​​for NMOS transistors...

AI Technical Summary

Problems solved by technology

As mentioned above, Al begins to diffuse above 350°C, and many process steps in the current back-end process (BEOL) exceed 350°C, therefore, Al will inevitably diffuse to the underlying PMOS work function metal layer 15 , thereby affecting the work function value of the PMOS work function metal layer 15

[0014] In order to prevent Al from diffusing into the PMOS work function metal layer 15, an additional barrier layer can be added between the PMOS work function metal layer 15 and the NMOS work function metal layer 16 to prevent the diffusion of Al. However, at a more advanced process node, The size of the second gate opening 112 will become so small that there will not be enough space for the additional barrier layer

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