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Gate driving unit, gate driving circuit and display device

一种栅极驱动、驱动单元的技术，应用在栅极驱动电路及显示装置,栅极驱动单元领域，能够解决漏电、限制电路工作频率、增大栅极驱动电路的输出脉冲下降延迟等问题

Active Publication Date: 2016-04-06
TCL CHINA STAR OPTOELECTRONICS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the driving stage of the gate drive circuit, the control electrode potential of the low-level maintenance transistor in the existing circuit design cannot be completely pulled down to a low level, resulting in the existence of leakage
The leakage of the low-level maintenance transistor increases the rise and fall delays of the output pulse of the gate drive circuit, thereby limiting the increase in the operating frequency of the circuit.

Method used

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  • Gate driving unit, gate driving circuit and display device
  • Gate driving unit, gate driving circuit and display device
  • Gate driving unit, gate driving circuit and display device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0052] refer to figure 2 , in a specific implementation manner of the gate driving unit of the present invention, the input module 11 includes a first transistor T1 and a third transistor T3. Wherein, the gate of the first transistor T1 and the first pole are short-circuited as the pulse signal input terminal of the input module 11 for inputting the first pulse signal V i , the second pole of the first transistor T1 and the first pole of the third transistor T3 are connected to the first control node Q 1 , the second pole of the third transistor T3 is connected to the low-level node Q 3 , the gate of the third transistor T3 is used as the first pull-down control terminal of the input module 11 for inputting the first control signal V c .

[0053] The output module 12 includes a second transistor T2, and further includes a first capacitor C1. Wherein, the gate of the second transistor T2 serves as the drive control terminal of the output module 12 and is connected to the f...

Embodiment 2

[0068] refer to Figure 5 , Figure 5 It is a schematic diagram of a specific circuit structure of another embodiment of the gate driving unit of the present invention. and figure 2 The main difference between the illustrated embodiments is that in this embodiment, the control module 13 further includes a fifteenth transistor T15. Wherein, the gate of the fifteenth transistor T15 is connected to the gate of the first transistor T1, and the first pole of the fifteenth transistor T15 is connected to the second control node Q 2 , the second pole of the fifteenth transistor T15 is connected to the low-level node Q 3 .

[0069] The gate of the fifteenth transistor T15 is controlled by the first pulse signal V i control. By adding the fifteenth transistor T15, at time t1, the first pulse signal V i The high-level control signal of the fifteenth transistor T15 is turned on, so that the second control node Q 2 Potential V Q2 quickly pulled low to V L , further suppressing t...

Embodiment 3

[0072] refer to Figure 6 , Figure 6 It is a schematic diagram of a specific circuit structure of another embodiment of the gate driving unit of the present invention. In this embodiment, with figure 2 The main difference of the illustrated embodiment is that the control module 13 further includes a ninth transistor T9 and a tenth transistor T10. The gate driving unit further includes a second low-level sustaining module 15, wherein the second low-level sustaining module 15 includes an eleventh transistor T11 and a twelfth transistor T12.

[0073] Wherein, the gate of the ninth transistor T9 is connected to the gate of the fourth transistor T4, the first pole of the ninth transistor T9 is used to input the third clock signal EXCK, the second pole of the ninth transistor T9 is connected to the gate of the tenth transistor T10 The first electrode, the gate of the eleventh transistor T11 and the gate of the twelfth transistor T12 are all connected to the fourth control node ...

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Abstract

The invention discloses a gate driving unit, a gate driving circuit and a display device, wherein a control module is disposed in the gate driving unit and used to bring down an electric potential of a second control node to a low level before or when an output module outputs a gate gating signal, so that an electric potential of a second dropdown control end of a low level maintenance module can be to a low level before and when the output module outputs the gate gating signal and thus the low level maintenance module stays at a cut-off state. In this way, the gate driving unit, gate driving circuit and display device disclosed by the invention can reduce electricity leakage possibility of the low level maintenance module, so that delaying of grating signal output can be reduced easily, and working efficiency can be increased.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to a gate drive unit, a gate drive circuit and a display device. Background technique [0002] Flat Panel Display (FPD, Flat-Panel-Display) has the advantages of high image definition, no flicker, energy saving, environmental protection, light and thin, etc., and is currently the mainstream display. In recent years, flat panel displays are developing toward high frame rates, high resolutions, and narrower bezels. [0003] In the driving method of flat panel displays, for example, for flat panel liquid crystal displays, the traditional driving method is to use an integrated circuit (IC), and the peripheral driving circuit is connected to the On the liquid crystal panel, this method is not conducive to the thinning and lightening of the display, and the cost is high. When the number of pins of the peripheral driving circuit is large, it will also affect the mechanical and el...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G09G3/36
CPCG09G3/3674G09G3/3677G09G2300/0408G11C19/28G09G3/3648G09G2310/0286G09G2310/0289G09G2310/08G09G2320/0252G09G2320/0214G09G2230/00
Inventor 张盛东胡治晋廖聪维曹世杰李长晔
Owner TCL CHINA STAR OPTOELECTRONICS TECH CO LTD
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