Semiconductor package with heat sink and packaging method thereof

Abstract

The invention discloses a semiconductor package with a cooling fin, and the semiconductor package comprises a lead frame. The lead frame comprises a chip carrier and a plurality of bent pins, wherein the plurality of bent pins are electrically connected with the chip carrier, and each pin comprises a pin surface, is parallel to the chip carrier and continuously extends between the chip carrier and the pin surface. The semiconductor package also comprises a chip installed on the chip table; a source electrode metal piece and a grid electrode metal piece, which are arranged in an insulated and isolated manner, wherein one plane of the source electrode metal piece and one plane of the grid electrode metal piece are respectively connected with a source electrode metal layer and a grid electrode metal layer of the chip in an all-surface manner, and the opposite planes of the source electrode metal piece and the grid electrode metal piece share one plane with the pin surface; and a package body which enables the lead frame, the chip, the source electrode metal piece and the grid electrode metal piece to be packaged. The semiconductor package can increase the effective connection area of the source electrode, so as to reduce the conducting resistance and grounding resistance. The semiconductor package reduces the power loss, is low in cost, and is small in package size.

Description

technical field [0001] The invention relates to a semiconductor packaging technology, in particular to a semiconductor packaging with a heat sink and a packaging method thereof. Background technique [0002] Heat dissipation semiconductor packages in the prior art, such as figure 1 Shown: A chip 2' with surface treatment is flipped on the lead frame 1', and a copper sheet 3' is welded on the top again. After a special plastic packaging process, the copper sheet is exposed outside the plastic package 5'. After this process The top and bottom of the processed product have dual channels for heat dissipation. [0003] In the products in the prior art, the surface of the chip 2' needs to be treated, and the value ball 4' is used to prevent the overflow of the adhesive material under the chip 2', and a certain space 6' needs to be reserved between the bottom source and drain It is used to isolate the source and drain to prevent the short circuit between the source and the drain,...

AI Technical Summary

Problems solved by technology

Therefore, processing the chip 2' leads to an increase in product cost, complicated work flow, and reduces the effective connection area of ​​the source electrode of the chip 2'

The reserved space of 6' reduces the effective space utilization of the entire product

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