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Fabrication method of interconnection medium layer, interconnection medium layer and fabrication method of interconnection layer

A manufacturing method and dielectric layer technology, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device parts, semiconductor devices, etc., can solve the problem of reducing the isolation performance of interconnection dielectric layers, reducing the SiCN barrier layer 10' and low dielectric Problems such as bonding strength and large lattice mismatch between material layers 30

Active Publication Date: 2019-01-08
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, due to the large lattice mismatch between the SiCN barrier layer 10' and the low dielectric material layer 30, greater stress is generated between the SiCN barrier layer 10' and the low dielectric material layer 30, thereby reducing the SiCN The bonding strength between the barrier layer 10' and the low dielectric material layer 30 reduces the isolation performance of the interconnect dielectric layer
At present, there is no effective solution to the above problems

Method used

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  • Fabrication method of interconnection medium layer, interconnection medium layer and fabrication method of interconnection layer
  • Fabrication method of interconnection medium layer, interconnection medium layer and fabrication method of interconnection layer
  • Fabrication method of interconnection medium layer, interconnection medium layer and fabrication method of interconnection layer

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Embodiment 1

[0051] This embodiment provides a method for fabricating an interconnection layer, including the steps of forming an interconnection dielectric layer, etching the interconnection dielectric layer to form a through hole with a damascene shape, and forming Cu in the through hole. Wherein, the step of forming the interconnection medium layer includes:

[0052] Forming a SiCN layer on the semiconductor substrate, wherein the height of the SiCN layer is 60nm;

[0053] The SiC layer is formed on the SiCN layer by an in-situ deposition process. The specific process parameters are: the flow rate of organosilane is 100 sccm, the flow rate of helium is 100 sccm, the power of the deposition reaction is 100w, and the time of the deposition reaction is 60s; the formed The height of the SiC layer is 15 nm.

[0054] Oxygen plasma treatment is performed on the SiC layer. The specific process parameters are: the flow rate of oxygen is 100 sccm, the flow rate of helium is 100 sccm, the power o...

Embodiment 2

[0063] This embodiment provides a method for fabricating an interconnection layer, including the steps of forming an interconnection dielectric layer, etching the interconnection dielectric layer to form a through hole with a damascene shape, and forming Cu in the through hole. Wherein, the step of forming the interconnection medium layer includes:

[0064] Forming a SiCN layer on the semiconductor substrate, wherein the height of the SiCN layer is 60nm;

[0065] The SiC layer is formed on the SiCN layer by an in-situ deposition process. The specific process parameters are: the flow rate of organosilane is 3000 sccm, the flow rate of helium is 3000 sccm, the power of the deposition reaction is 4000w, and the time of the deposition reaction is 5s; The height of the SiC layer is 60 nm.

[0066] Oxygen plasma treatment is performed on the SiC layer. The specific process parameters are: the flow rate of oxygen is 100-3000sccm, the flow rate of helium is 100-3000sccm, the power of...

Embodiment 3

[0069] This embodiment provides a method for fabricating an interconnection layer, including the steps of forming an interconnection dielectric layer, etching the interconnection dielectric layer to form a through hole with a damascene shape, and forming Cu in the through hole. Wherein, the step of forming the interconnection medium layer includes:

[0070] Forming a SiCN layer on the semiconductor substrate, wherein the height of the SiCN layer is 60nm;

[0071] The SiC layer is formed on the SiCN layer by an in-situ deposition process. The specific process parameters are: the flow rate of organosilane is 1200 sccm, the flow rate of helium is 1500 sccm, the power of the deposition reaction is 2000w, and the time of the deposition reaction is 20s; the formed The height of the SiC layer is 50 nm.

[0072] Oxygen plasma treatment is performed on the SiC layer. The specific process parameters are: the flow rate of oxygen is 1200 sccm, the flow rate of helium is 1500 sccm, the po...

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Abstract

The application discloses a manufacturing method of an interconnection dielectric layer, an interconnection dielectric layer and a manufacturing method of an interconnection layer. The manufacturing method of an interconnection dielectric layer comprises: a barrier layer is formed, wherein the barrier layer is silicon-contained carbide; a SiC layer is formed on the barrier layer; oxidation processing is carried out on the SiC layer, thereby forming a SiO2 layer at one side, far away from the barrier layer, of the SiC layer; and a low-dielectric material layer is formed on the SiO2 layer. According to the manufacturing method, because the SiC layer and lattices of the SiC layer and the barrier layer match and lattices of the SiO2 layer and the low-dielectric material layer match, thereby reducing the stress caused by lattice mismatching between the barrier layer and the low-dielectric material layer and thus improving the bonding strength between the barrier layer and the low-dielectric material layer and improving the isolation performance of the interconnection dielectric layer.

Description

technical field [0001] The present application relates to the technical field of semiconductor integrated circuits, and in particular, to a method for manufacturing an interconnection medium layer, an interconnection medium layer and a method for making an interconnection layer. Background technique [0002] The interconnection layer generally includes an interconnection metal layer electrically connected to the semiconductor base and an interconnection medium layer disposed between the interconnection metal layers. Among them, the interconnected metal layers are usually arranged along a direction parallel to the semiconductor base, and different interconnected metal layers are formed in a direction perpendicular to the semiconductor base through embedded structures (including through holes and metal materials disposed in the through holes) to form electrical connections. connect. The above-mentioned interconnection medium layer is generally an electrical insulating materia...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L23/532
Inventor 周鸣
Owner SEMICON MFG INT (SHANGHAI) CORP