Routing method and system for non-regular three-dimensional integrated circuit network-on-chip

Abstract

The invention provides a routing method and system for a non-regular three-dimensional integrated circuit network-on-chip. The method comprises the steps of according to the topological structure of the non-regular three-dimensional integrated circuit network-on-chip, determining that a Hamiltonian path based error tolerance routing algorithm route data package or a spanning tree based error tolerance routing algorithm route data package is adopted; if the Hamiltonian path based error tolerance routing algorithm route data package is adopted, determining to perform routing error tolerance by use of the sequence of monotonous ascending node number or monotonous descending node number according to positions of a source node and a destination node; and if the spanning tree based error tolerance routing algorithm route data package is adopted, selecting to generate a tree root node, and selecting a transmission path to finish transmission of the data package according to the root node and positions of the source node and the destination node.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a routing method and system for an irregular three-dimensional integrated circuit on-chip network. Background technique [0002] Three-dimensional integration technology is a packaging technology that stacks different device layers of a chip and vertically integrates them together (BanerjeeK, et al., "3-DICs: novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration," in Proceeding of the IEEE, Volume: 89, Issue: 5, 2001, pp.602-633.). This technology can shorten the length of the physical connection in the chip, so as to reduce the system delay and power consumption. figure 1 It is a schematic diagram of a simple 4*2*3 three-dimensional chip network (network-on-chip, NoC), and the topology is a common three-dimensional Mesh structure. In the figure, there are 3 different device layers, and 24 processing elements (pr...

AI Technical Summary

Problems solved by technology

The use of virtual channels will introduce large area overhead and complex control logic, which is not suitable for circuit design with strict overhead requirements

[0010] 2) Even if the virtual channel technology is not used, but a low-cost steering model is adopted, or a new theory is introduced to avoid deadlocks, other problems may also be caused. For example, due to the irregular network structure, a single steering model will lead to The routing algorithm guided by it cannot be executed, and the introduction of multiple steering models requires the support of VC technology; in addition, there are hidden dangers in simply introducing some special path routing data packets, that is, in many irregular 3D on-chip networks. Unable to find a special path that matches the criteria

[0011] 3) The port selection mechanism of many existing solutions adopts a random selection strategy, that is, a port is randomly selected to output data packets when the legal port is not unique, which cannot bypass the conflict area well, resulting in low network communication performance

[0012] The above three points directly lead to three major defects in the existing achievements: first, high communication performance (mainly including two indicators of communication delay and throughput rate) cannot be guaranteed; second, the reliability index of communication is low; third, , higher system overhead

Images