[0035] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.
[0036] figure 1 It is a schematic diagram of the structure composition of the multiplier used in the RFID security chip of the embodiment of the present invention, such as figure 1 As shown, the multiplier includes:
[0037] Partial product generating circuit 1 is used to generate partial products and input the partial products to the compression circuit;
[0038] The compression circuit 2 is used to receive the partial product generated by the partial product generation circuit 1, obtain compressed temporary variables for the partial product compression processing, and input the temporary variables to the carry propagation adder 3;
[0039] The carry propagation adder 3 is used to compress temporary variables and obtain the multiplication result.
[0040] figure 2 Shows the structure of another embodiment of the multiplier of the present invention, such as figure 2 As shown, the compression circuit 2 further includes:
[0041] The first stage compression circuit 20 is configured to receive the partial product generated by the partial product generation circuit, compress the partial product, obtain a first temporary variable, and input the first temporary variable to the second stage compression circuit 21;
[0042] The second-stage compression circuit 21; for receiving the first temporary variable, and compressing the first temporary variable to obtain the second temporary variable, and input the second temporary variable to the third-stage compression circuit 22;
[0043] The third-stage compression circuit 22 is configured to receive the second temporary variable, perform compression processing on the second temporary variable, obtain the third temporary variable, and input the third temporary variable into the fourth-stage compression circuit 23;
[0044] The fourth stage compression circuit 23 is used for receiving the third temporary variable, compressing the third temporary variable, obtaining intermediate data, and inputting the intermediate data to the carry propagation adder 3.
[0045] Combine below image 3 , Figure 4 The multiplier of the embodiment of the present invention will be further described.
[0046] The structure of the hybrid compression tree in the multiplier is as follows figure 2 As shown, the compression tree is composed of a mixture of 4-2 and 5-2 compressors. There are a total of 4 stages of compression circuits. The first, second, and fourth stages of compression circuits are composed of 4-2 compressors, and the third stage of compression circuits is composed of 4-2 compressors. Composed of 5-2 compressors, the main purpose of this hybrid design is to reduce the critical path of the compression tree. The 4-2 compressor has a 2-stage full adder delay, and its function is to compress the 4 partial products into 2 temporary variables. The 5-2 compressor has a 3-stage full adder delay, and its function is to compress the 5-item partial product into 3 temporary variables. The input of the compression tree is the 36-item partial product generated by the partial product generation circuit of the parallel multiplier, and the output is the compressed two-item results C and S, which are output to the next stage of carry propagation adder.
[0047] In specific implementation, the first-stage compression circuit 20 is composed of 9 4-2 compressors, which are used to compress 36 partial products into 18 temporary variables, and the 18 temporary variables are input to the second-stage compression circuit 21.
[0048] The second-stage compression circuit 21 is composed of 4 4-2 compressors, which are used to compress 16 temporary variables out of the 18 temporary variables compressed by the first-stage compression circuit 20 into 8 temporary variables, and combine 8 The temporary variable is input to the third stage compression circuit 22.
[0049] The third stage compression circuit 22 is composed of two 5-2 compressors, used to compress the 8 temporary variables compressed by the second stage compression circuit 21 and the remaining 18 temporary variables compressed by the first stage compression circuit The 2 temporary variables are compressed into 4 temporary variables, and the 4 temporary variables are input to the fourth stage compression circuit 23.
[0050] The fourth-stage compression circuit 23 is composed of a 4-2 compressor, which is used to compress the 4 temporary variables compressed by the third-stage compression circuit 22 into 2 intermediate data, and input the 2 intermediate data to carry propagation Adder 3.
[0051] The multiplier is mainly divided into serial and parallel multipliers from the operation mode. The generation and accumulation of partial products of serial multipliers are executed in sequence, which consumes less resources, and is suitable for occasions that require relatively high chip area. The parallel operation method trades area for speed, and uses a large number of operation components to generate and accumulate partial products at the same time. This method is usually used in the design of high-performance multipliers. The way to increase the operation speed of the multiplier is to use the tree structure to reduce the number of summation series. The Wallace tree is the most famous one, and it is particularly suitable for the design of multipliers with more than 16 bits.
[0052] The present invention is mainly used for integration into high-speed parallel multipliers, usually as Figure 4 Shown. The main function of the multiplier is to perform multiplication operations: P=X*Y. It is mainly composed of Booth encoder, Booth decoder, hybrid compression and final carry propagation adder.
[0053] The basic working principle of the parallel multiplier can be described as follows. Firstly, Booth encoder performs Booth coding on multiplier X according to Booth coding algorithm, and then Booth selector will select Booth coding according to multiplicand Y and produce 36 partial product output. The hybrid compression tree proposed by the present invention compresses the two intermediate data C and S in the 36-item partial product. The compression tree of the present invention reduces the critical path delay and improves the overall operating speed of the multiplier. The final carry propagation adder compresses the intermediate data C and S produced by the compressor into the final multiplication result output P. The partial product generation circuit of this structure multiplier adopts Booth coding structure, and the number of partial products generated by it is half of the traditional multiplier. In the partial product compression stage, a hybrid Wallace compression tree structure is used to perform fast parallel compression processing on the generated partial products, which effectively improves the speed of partial product compression. In the circuit structure, partial product generation and partial product compression adopt a parallel rehearsal structure, which greatly improves the speed of partial product generation.
[0054] Correspondingly, the embodiment of the present invention also provides a method for implementing a multiplier for an RFID security chip, such as Figure 5 As shown, the method includes:
[0055] S51, generate a partial product, and input the partial product to the compression circuit;
[0056] S52: The compression circuit receives the partial product generated by the partial product generation circuit, compresses the partial product to obtain the compressed temporary variable, and inputs the temporary variable to the carry propagation adder;
[0057] S53, the carry propagation adder compresses the temporary variable and obtains the multiplication result.
[0058] Further, S52 includes:
[0059] The first stage compression circuit receives the partial product generated by the partial product generation circuit, compresses the partial product, obtains the first temporary variable, and inputs the first temporary variable to the second stage compression circuit;
[0060] The second stage compression circuit receives the first temporary variable, compresses the first temporary variable, obtains the second temporary variable, and inputs the second temporary variable to the third stage compression circuit;
[0061] The third-stage compression circuit receives the second temporary variable, performs compression processing on the second temporary variable, obtains the third temporary variable, and inputs the third temporary variable to the fourth-stage compression circuit;
[0062] The fourth stage compression circuit receives the third temporary variable, compresses the third temporary variable, obtains intermediate data, and inputs the intermediate data to the carry propagation adder.
[0063] The first-stage compression circuit consists of 9 4-2 compressors, which compress the 36-item partial products generated by the partial-product generation circuit into 18 temporary variables, and input the 18 temporary variables to the second-stage compression circuit.
[0064] The second stage compression circuit is composed of 4 4-2 compressors, which compresses 16 temporary variables out of the 18 temporary variables compressed by the first stage compression circuit into 8 temporary variables, and inputs the 8 temporary variables into The third stage compression circuit.
[0065] The third stage compression circuit is composed of two 5-2 compressors, which compress the 8 temporary variables compressed by the second stage compression circuit and the remaining 2 temporary variables among the 18 temporary variables compressed by the first stage compression circuit Compressed into 4 temporary variables, and input the 4 temporary variables to the fourth stage compression circuit.
[0066] The fourth stage compression circuit is composed of a 4-2 compressor, which compresses the 4 temporary variables compressed by the third stage compression circuit into 2 intermediate data, and inputs the 2 intermediate data to the carry propagation adder 3.
[0067] For the process processing in the method embodiment of the present invention, refer to the function of each functional module in the embodiment of the present invention, which will not be repeated here.
[0068] In the embodiment of the present invention, the number of summation stages in the tree structure is reduced by the hybrid compression tree, which can reduce the critical path of the multiplier compression tree, reduce the circuit delay, and increase the operating speed of the security chip, which is suitable for integration into the smart card chip RSA or ECC coprocessor to improve the working speed of the coprocessor.
[0069] Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above-mentioned embodiments can be completed by a program instructing relevant hardware. The program can be stored in a computer-readable storage medium, and the storage medium can include: Read only memory (ROM, ReadOnlyMemory), random access memory (RAM, RandomAccessMemory), magnetic disk or optical disk, etc.
[0070] In addition, the multiplier and implementation method for the RFID security chip provided by the embodiments of the present invention are described in detail above. Specific examples are used in this article to illustrate the principle and implementation of the present invention. The description of the above embodiments is only It is used to help understand the method and core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation and the scope of application. In summary, the present The contents of the description should not be construed as limiting the present invention.
