Statistical timing analysis method used for post-silicon adjustable register circuits

Abstract

The invention belongs to the technical field of integrated circuits, and in particular relates to a statistical timing analysis method for a post-band silicon adjustable register circuit. The method includes: compressing the pivot to obtain N independent random variables; generating sparse grid configuration points; calculating the minimum clock period of each configuration point; calculating the minimum clock period generalized polynomial chaos expansion coefficient; calculating the post-silicon adjustable register circuit yield rate. The method has high feasibility, can significantly reduce the program running time while obtaining the accuracy comparable to the existing method, and can be used to solve the statistical timing analysis problem of large-scale post-band silicon adjustable register circuits.

Description

technical field

[0001] The invention belongs to the technical field of integrated circuits, and relates to a statistical timing analysis method for a post-band silicon adjustable register circuit. technical background

[0002] As IC feature sizes shrink below 100nm, process variation has become one of the major challenges to circuit timing performance. Post-silicon tunable clock tree is a powerful technique to fix timing violations caused by process variation [1,2]. In post-silicon tunable clock trees, post-silicon tunable registers are inserted into the clock tree during the design phase. The delay of the post silicon adjustable register can be adjusted by changing the control signal. A typical post-silicon tunable register structure such as figure 2 Shown in [1]. After the chip is produced, the time margin of the register state can be balanced by changing the delay of the post-silicon tunable register. This process is called post-silicon tuning. During post-silicon tu...

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