Method for reducing area of chip with inductor device in radio frequency technology and application
A technology of chip area and inductance, which is applied in the field of reducing the chip area of inductive devices in radio frequency technology, and can solve problems such as large increase in chip area, leakage, and large chip size
Inactive Publication Date: 2016-06-15
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology
[0005] This rule results in a larger chip size with inductors and thus a larger increase in chip area
[0006] Many customers' chips do not have very high requirements on the Q value of the inductor and signal crosstalk, but in order to reduce the chip cost and require a smaller area, they will change 45μm to a smaller value; but because Pwell will still be generated according to logic operations, so It is not generated in a large part of the customer's circuit, which will cause the leakage problem without Pwell isolation in the surrounding circuit of the inductor
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[0014] In order to make the purpose, features, and advantages of the present invention more obvious and understandable, the technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention.
[0015] The method for reducing the chip area of the inductive device in the radio frequency process is implemented in the following embodiments:
[0016] If the customer needs to reduce the distance between the inductance and the peripheral circuit in order to shrink the chip, then in the circuit design, the inductance calibration layer (INDID) will be correspondingly pointed to the inside of the inductance device. Shrink 20μm (45-25) to the inside of the inductor, so that after INDID+45μm, the resulting Pwell layer and the value of the circuit distance inductance are the same, which is equal to the customer's design value.
[0017] By adopting the above method, without modifying the logica...
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The invention discloses a method for reducing the area of a chip with an inductor device in a radio frequency technology. A customer reduces an INDID (inductance calibration layer) layer and arranges the reduced INDID layer into the inductor device when reducing the area of the chip and reducing the distance between the inductor and a peripheral circuit, so that a value meeting the requirements of the INDID layer and the process design rule is obtained; and then the distance between the inductor and the peripheral circuit is equal to the designed value of the customer.
Description
technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a method and application for reducing the chip area of an inductive device in a radio frequency process. Background technique [0002] Inductors are radio frequency devices used in radio frequency processes such as RFCMOS (Radio Frequency Complementary Metal Oxide Semiconductor) and SiGeBiCMOS (Silicon Germanium Bipolar-Complementary Metal Oxide Semiconductor) processes. [0003] In a chip with an inductance, in order to ensure its Q value and prevent signal crosstalk, the distance between the inductance and other circuits is relatively long; for example, it is defined as INDID (inductance calibration layer) + 45 μm, so that other devices will not be placed within 45 μm around the inductance device . [0004] Pwell (P well) is a layer generated by calculation. In addition to being used as an NMOS (N-type metal-oxide-semiconductor) device channel, it is also a l...
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IPC IPC(8): H01L21/8238H01L21/8249H01L27/02H01L29/06
CPCH01L21/823892H01L21/8249H01L27/0207H01L29/0638
Inventor 陈曦
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP