Metallization stack and semiconductor device and electronic equipment including same
A metallization and stacking technology, which is applied in semiconductor devices, semiconductor/solid-state device parts, electric solid-state devices, etc., can solve problems such as mechanical and electrical stability issues, etc.
Active Publication Date: 2019-02-15
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Problems solved by technology
One way to suppress this increase in capacitance is to use an air gap between interconnected parts, but there are problems with its mechanical and electrical stability
Method used
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[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.
[0014] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, ...
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Disclosed are a metallization stack and semiconductor devices and electronic equipment including the metallization stack. According to an embodiment, the metallization stack may include: an interlayer dielectric layer including a dielectric material and a negative capacitance material, wherein at least one pair of first conductive interconnect features formed in the interlayer dielectric layer are at least partially opposed to each other Including both a dielectric material and a negative capacitance material between their opposing portions, and / or at least one second conductive interconnect feature formed in an upper layer of the interlayer dielectric layer and a second conductive interconnect feature formed in a lower layer of the interlayer dielectric layer and At least one third conductive interconnect feature at least partially opposed by the second conductive interconnect feature includes both a dielectric material and a negative capacitive material between their opposing portions.
Description
technical field [0001] The present disclosure relates to semiconductor technology, and more particularly, to a metallization stack capable of reducing capacitance between conductive interconnection components and semiconductor devices and electronic devices including the metallization stack. Background technique [0002] As the density of devices in integrated circuits (ICs) continues to increase, the spacing between components is getting smaller and smaller. This increases the capacitance between conductive interconnection parts in the IC, especially interconnection wires, and thus degrades the performance of the IC. On the other hand, even for less performance-critical devices, low power consumption, and thus reduced capacitance, is desirable. One way to suppress this increase in capacitance is to use an air gap between interconnected parts, but there are problems with its mechanical and electrical stability. [0003] Therefore, there is a need to be able to continually ...
Claims
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IPC IPC(8): H01L23/522H01L27/00
CPCH01L23/5222H01L27/00H01L27/0629H01L23/5329H01L23/53295H01L23/528
Inventor 朱慧珑
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI