Method of forming memory device

Abstract

A method for forming a memory device, including: forming several overlapping composite layers on the surface of a substrate, with a mask layer on the surface of the composite layer, and the composite layer includes an insulating layer and a device layer located on the surface of the insulating layer; A reinforcement layer is formed on the side wall surface, and the reinforcement layer exposes the top surface of the mask layer and part of the side wall surface; using the reinforcement layer as a mask, the exposed side wall surface of the mask layer is etched, exposing part of the top composite layer surface; then, use the mask layer and strengthening layer as a mask to etch the exposed composite layer, and the etching thickness of the composite layer is greater than or equal to the thickness of the single-layer device layer; then, repeat the etching mask once or several times The steps of film layer sidewalls and etching the composite layer are until the projected pattern size of several device layers is gradually reduced in at least one direction from the bottom to the top layer, so that the several device layers form a ladder shape that decreases layer by layer from the bottom layer to the top layer. The formed storage device has low space occupation rate, high bit density and low bit cost.

Description

technical field [0001] The present invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a storage device Background technique [0002] In recent years, the development of flash memory (flash memory) is particularly rapid. The main feature of flash memory is that it can keep stored information for a long time without power on, and has the advantages of high integration, fast access speed, easy erasing and rewriting, etc. Has been widely used. In order to further increase the bit density of the flash memory while reducing the bit cost, a three-dimensional NAND (3D NAND) flash memory is proposed. [0003] Please refer to figure 1 , figure 1 It is a structural schematic diagram of an existing three-dimensional NAND gate flash storage unit, including: a substrate 100; an isolation layer 103 located on the surface of the substrate 100; a bottom selection gate 104 located on the surface of the isolation layer 103; Sever...

AI Technical Summary

Problems solved by technology

[0005] However, the space occupied by the existing 3D NAND gate flash storage unit is still relatively large, and it is necessary to further reduce the space utilization of the 3D NAND flash memory storage unit, further increase the bit density, and reduce the bit cost.

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