Fan-out type wafer-level packaging method for semiconductor device
A wafer-level packaging and fan-out technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., can solve the difficulty of controlling the dimensional accuracy of rewiring layer thickness and width, and the difficulty of ensuring the flatness of the front of the chip , poor heat dissipation performance and other problems, to achieve the effect of ensuring flatness, improving heat dissipation performance, and improving precision
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[0022] In order to solve the above-mentioned problems in the prior art, the present invention provides a fan-out wafer-level packaging method for semiconductor devices. The chip and the first wafer are bonded directly or through an intermediate layer, and the bonding state is maintained, without the need for The first wafer is separated and removed in the subsequent process, so the pad on the front of the chip does not need to be opened before bonding, which can effectively ensure the flatness of the chip, improve the accuracy of the redistribution layer, and use the planarization technology to make the back of the chip and the filling material The surface is flattened to reduce the package height and improve the heat dissipation performance.
[0023] In the following detailed description of the preferred embodiments, reference will be made to the attached drawings constituting a part of the present invention. The attached drawings illustrate specific embodiments capable of imple...
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