Fan-out type wafer-level packaging method for semiconductor device

Abstract

The invention provides a fan-out type wafer-level packaging method for a semiconductor device, and the method comprises the steps: providing a first wafer, and pasting a plurality of chips on the first surface of the first wafer, wherein the front surfaces of the chips are directly bonded with the first wafer or through a central layer; placing filling materials between the chips, and enabling the back surfaces of the chips and the surfaces of the filling materials to be flattened through the flattening technology; enabling the surfaces of the filling materials and the back surfaces of the chips to be directly bonded with a second wafer or through a central layer, and reducing the thickness of the first wafer to a preset thickness from the second surface of the first wafer; forming at least one rewiring layer on the second surface of the first wafer, and forming a welding ball on the outermost rewiring layer. The method provided by the invention can effectively guarantee the flatness of the chips, improves the precision of the rewiring layers, enables the back surfaces of the chips and the surfaces of the filling materials to be flattened through the flattening technology, reduces the packaging height, and improves the heat dissipation performance.

Description

technical field [0001] The invention relates to the field of chip packaging, in particular to a fan-out wafer-level packaging method for semiconductor devices. Background technique [0002] In the traditional fan-in wafer level packaging (Fan-inWafer Level Packaging) process, the semiconductor device chips in the wafer are packaged before the step of cutting the wafer, and the I / O ports and other components of the chip package are controlled by the chip Area limits defined by edges. [0003] With the vigorous development of the electronics industry, electronic products are developing toward multi-functional and high-performance trends. Chip packages have more I / O ports, smaller package sizes, and higher requirements for integration flexibility. Wafer level packaging (Fan-out Wafer Level Packaging) technology. Fan-out wafer-level packaging can be applied to chip packages with a large number of I / O ports, and is not limited by chip size. [0004] The existing fan-out wafer ...

AI Technical Summary

Problems solved by technology

[0005] However, the existing fan-out wafer-level packaging method has the following disadvantages: on the one hand, since the carrier wafer needs to be removed later to expose the pads on the front side of the chip, the pads should be pre-bonded with the carrier wafer before temporary bonding. Open, so that when the front of the chip and the surface of the carrier wafer are bonded by temporary bonding glue, the flatness of the front of the chip is difficult to guarantee, so when the rewiring layer is formed on the front of the chip, the dimensional accuracy of the thickness and width of the rewiring layer Difficult to control; on the other hand, the plastic packaging material layer wraps the chip in it, resulting in a thicker overall package height and poor heat dissipation performance

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