Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a silicon substrate, a protective layer, a bonding pad, an insulating layer, a wiring layer, a conductive layer, a barrier layer, and a conductive structure. The silicon substrate has a hollow area, a ladder structure, a sharp corner structure, and opposite first and second surfaces. The ladder structure and the sharp corner structure are around the hollow area. The ladder structure has a first inclined surface, a second inclined surface and a third inclined surface, and the first inclined surface, the second inclined surface and the third inclined surface face the hollow area and are connected in order. The protective layer is at the first surface of the silicon substrate. The bonding pad is in the protective layer and is exposed from the hollow area. The insulating layer is on the first inclined surface, the third inclined surface, the second inclined surface, the second surface, and the sharp corner structure. The wiring layer is on the insulating layer and the bonding pad. The conductive layer is on the wiring layer. The barrier layer covers the ladder structure and the sharp corner structure. The conductive structure is on the conductive layer in the opening on the barrier layer. According to the semiconductor structure and the manufacturing method, the yield of the semiconductor structure can be improved, and the convenience of material selection can be improved.

Description

technical field [0001] The invention relates to a semiconductor structure and a manufacturing method of the semiconductor structure. Background technique [0002] The existing semiconductor structure may include a chip, a bonding pad, a dielectric layer (such as silicon dioxide), a wiring layer (Redistribution Layer; RDL), a conductive layer, a barrier layer and solder balls. Generally speaking, when fabricating a semiconductor structure, a dielectric layer is covered on a silicon substrate (wafer) that has not been cut into wafers to protect electronic components (such as photosensitive components) on the silicon substrate. Then, the silicon substrate and the dielectric layer above the welding pad in the dielectric layer can be removed by photolithography and etching process, so that the silicon substrate and the dielectric layer form a via, and the welding pad is exposed through the via hole. . [0003] Afterwards, an insulating layer can be covered on the surface of the...

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Problems solved by technology

[0004] However, since the surface slope of the silicon substrate around the via hole is steep, that is, the via aspect ratio of the via hole is large, the wiring layer and the conductive layer are prone to breakage at the turning point of the silicon substrate adjacent to the via hole, resulting in a good semiconductor structure. It is difficult to increase the rate

In addition, in order to reduce the aspect ratio of the through hole, although a thinner silicon substrate can be used, a thicker silicon substrate cannot be used, causing inconvenience to the designer

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