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Multilevel multitask parallel decoding algorithm on multicore processor platform

A multi-core processor and decoding algorithm technology, which is applied in the field of multi-level multi-task parallel decoding algorithm, achieves the effects of reducing frequent scheduling and switching, improving parallelism, and high engineering application value

Active Publication Date: 2016-10-05
NANJING UNIV OF POSTS & TELECOMM
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Problems solved by technology

[0005] The technical problem to be solved by the present invention is that, on the premise of ensuring the quality of the decoded image, the real-time decoding of the high-definition single code stream formed without any parallel encoding method greatly improves the decoding parallel acceleration ratio

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[0025] Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail:

[0026] The invention realizes the real-time parallel decoding of HEVC high-definition video aiming at the ultra-high parallel computing performance of the multi-core processor. We will use the Tilera GX36 multi-core processor as our experimental platform, which consists of 36 Tile cores. The Tilera multi-core processor has a complete set of multi-core development tools, which provides convenience for us to implement multi-core parallel programs.

[0027] figure 1 Shown is the HEVC decoder block diagram. The basic structure of the HEVC encoding and decoding principle is basically the same as that of H.264 / AVC, but the performance improvement of the HEVC encoding and decoding comes from a series of in-depth optimizations at the module level and innovations in some design elements. Among them, the new features that are more important for the perform...

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Abstract

The invention discloses a multilevel multitask parallel decoding algorithm on a multicore processor platform, and provides the multilevel multitask parallel decoding algorithm for effective combination of tasks and data on the multicore processor platform by utilizing the dependency of HEVC data by aiming at the problems of mass data volume of high-definition videos and ultrahigh processing complexity of HEVC decoding. HEVC decoding is divided into two tasks of frame layer entropy decoding and CTU layer data decoding which are processed in parallel by using different granularity; the entropy decoding task is processed in parallel in a frame level mode; the CTU data decoding task is processed in parallel in a CTU data line mode; and each task is performed by an independent thread and bound to an independent core to operate so that the parallel computing performance of a multicore processor can be fully utilized, and real-time parallel decoding of HEVC full high-definition single code stream using no parallel coding technology can be realized. Compared with serial decoding, the decoding parallel acceleration rate can be greatly enhanced and the decoding image quality can be guaranteed by using the multicore parallel algorithm.

Description

technical field [0001] The invention relates to the field of encoding and decoding of digital video signals, in particular to a multi-level and multi-task parallel decoding algorithm on a multi-core processor platform. Background technique [0002] With the development of mobile Internet and the continuous progress of Internet video applications, in order to meet people's continuous demand for high-definition (HD) and other videos, in 2010, JCT-VC, an international video coding standard organization jointly established by MPEG and VCEG, jointly developed a new generation of video The encoding international standard HEVC (High Efficiency Video Coding) officially became an international standard in January 2013. The goal of "high-efficiency coding" HEVC is to improve video coding efficiency. Under the premise of the same image quality, the compression rate is double that of H.264 / AVC high profile. Considering the huge data volume of high-definition video encoding and decoding...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N19/44H04N19/436
Inventor 胡栋方狄束骏
Owner NANJING UNIV OF POSTS & TELECOMM
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