A low on-resistance lateral double-diffused metal oxide semiconductor device

Abstract

A low on-resistance lateral double-diffused metal oxide semiconductor device, comprising: a P-type substrate, a high-voltage N-type region is arranged above the P-type substrate, and an N-type drift region and an N-type drift region are arranged above the high-voltage N-type region. In the P-type body region, an N-type drain region and a shallow trench isolation region are arranged in the N-type drift region, an N-type source region and a P-type region are arranged in the P-type body region, and a gate is arranged above the high-voltage N-type region. The two ends of the gate oxide layer extend to the top of the P-type body region and the first shallow trench isolation region respectively, and a polysilicon gate field plate is arranged above the gate oxide layer, and the N-type drain region and the N-type source region There is a metal contact with the P-type region. It is characterized in that the shallow trench isolation region includes a first shallow trench isolation region and a second shallow trench isolation region arranged at intervals and symmetrically, and the two ends of the second shallow trench isolation region are retracted and shorter than the first shallow trench isolation region. Slot isolation area. The invention can obtain extremely low on-resistance on the basis of almost constant breakdown voltage.

Description

technical field [0001] The invention relates to the field of power semiconductor devices, and relates to a lateral double-diffused metal oxide semiconductor device with low conduction resistance. Background technique [0002] With the rapid development of semiconductor technology and its application fields, the manufacturing process and structure of power semiconductor devices are constantly improving, which promotes the development of power devices in the direction of high performance. [0003] Among power devices, Lateral Double-Diffused MOSFET (LDMOS for short) has the advantages of high withstand voltage, high input impedance and easy integration, so it is widely used in the manufacture of semiconductor integrated circuits. Compared with conventional MOSFETs, LDMOS devices have a low-doped drift region. When a high voltage is applied between the drain and the source, since the drift region has a high resistance, most of the voltage is applied to the drift region, which ...

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Problems solved by technology

However, studies have shown that when conventional STI is used as the field plate medium in the LDMOS drift region, the linear region current on the LDMOS conductive path is greatly affected by STI. Due to the limitation of the size of the STI structure, the withstand voltage and on-resistance of LDMOS cannot be achieved. optimization, so it is difficult to achieve low on-resistance LDMOS

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