System and method for testing digital-analog mixed signal chip

A technology of chip testing and digital-analog mixing, which is applied in the field of digital/analog and analog/digital converter chip testing systems, can solve problems such as poor reliability and stability, reduced authenticity of test data, and large amount of repetitive labor. Increase reliability and stability, ensure test validity, and save circuit cost

Active Publication Date: 2016-10-26
HEFEI CHIPSEA ELECTRONICS TECH CO LTD
View PDF5 Cites 31 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, although the application uses the ARM processor for testing, it is not suitable for digital / analog and analog / digital test systems, and the test still requires external equipment, which has a high cost; at the same time, the test data is not reliable
[0004] Therefore, the current D / A and A / D test devices have poor reliability and stability when performing digital-to-analog conversion, and it is difficult to implement dynamic testing. It is necessary to build circuits and external equipment, which reduces the authenticity of test data to a certain extent. Digital / analog and analog / digital module tests need to rebuild the test platform, resulting in poor versatility, and cannot automatically detect whether the chip is online and judge whether the tested chip is in good contact. Only a single chip can be tested, which requires a lot of repetitive labor. The software layered design is relatively simple, the modularization and reusability design is not complete, the coupling between modules is too strong, and the program cannot be transplanted quickly, and each development will cause a serious waste of manpower, material resources and time resources. The maintenance complexity is high, and it is very urgent to design a stable and dynamic digital / analog and analog / digital test system to accurately test and verify that the real performance indicators of digital / analog and analog / digital are provided to designers

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • System and method for testing digital-analog mixed signal chip
  • System and method for testing digital-analog mixed signal chip
  • System and method for testing digital-analog mixed signal chip

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0045] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0046] figure 1 Shown is the structural representation of the system realized by the present invention. As shown in the figure, the test device can test the digital / analog and analog / digital modules in addition to the MCU and the dedicated DAC and ADC with built-in digital-analog modules; On the other hand, it can be used as a system to display chip performance parameters to customers who use the chip. By operating a PC, it can display 12-digit / analog and analog / digital chip performance parameters to designers or customers.

[0047] The digital / analog and analog / digital chip test system developed ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a system and a method for testing a digital-analog mixed signal chip. The system comprises a USB communication module, an online detection module, a DAC measurement module, a display alarm module, a linear scanning module and an error processing module, and is characterized in that the modules are all integrated in an ARM processor. The system and the method disclosed by the invention have functions of multi-chip online detection, automatic and manual combination, real-time data recording and storage, system error processing and the like, the hardware cost is saved, and the software design cycle is shortened. Meanwhile, the system and the method can also avoid unstable factors brought about by an externally lapping circuit.

Description

technical field [0001] The invention belongs to the technical field of chip testing, in particular to a chip testing system and method for digital / analog and analog / digital converters. Background technique [0002] With the expansion of product application fields, high requirements are placed on the performance indicators of 12-bit analog-to-digital converters (DAC) and digital-to-analog converters (ADC). Traditional digital / analog and analog / digital chip test systems are limited in operability and poor versatility. Dynamic testing of digital / analog and analog / digital parameters requires external equipment, which is costly; the external circuit is unstable and the test data is not stable. Reliable; there is no special control software test data that needs to be manually recorded, the labor cost and time cost are high, and the repetitive workload is large; there is no more general digital-analog chip test system. [0003] Patent application 201310666255.7 discloses an LCM te...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10
CPCH03M1/1071
Inventor 庞新洁
Owner HEFEI CHIPSEA ELECTRONICS TECH CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products