A Method of Optimizing Wafer Edge Defects for CMOS Image Sensors

Abstract

The invention provides a method for optimizing wafer edge defects of a CMOS image sensor. The method comprises the following steps of: obtaining a plurality of wafers of a CIS product to be manufactured, wherein silicon oxide layers grows on the backs of the wafers; for the plurality of wafers of the CIS product to be manufactured, growing silicon nitride layers on the silicon oxide layers of the plurality of wafers with a furnace tube method as hard masks for subsequent etching; and carrying out shallow trench etching on the plurality of wafers.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, and more specifically, the invention relates to a method for optimizing the edge defects of a CMOS image sensor wafer. Background technique [0002] CIS (CMOS Image Sensor, CMOS image sensor device) is a photoelectric conversion device that uses a row of built-in LED light-emitting diodes for illumination. Because of its small size and light weight, it is widely used in mobile devices such as smartphones with camera functions middle. [0003] The camera function of the contact sensor is particularly sensitive to the increase of electric leakage and white spots caused by metal pollution, especially the pollution of the working area, which leads to low yield and even scrapping of a large number of wafers. [0004] In order to prevent metal ion contamination on the back of the wafer during the process, a layer of silicon oxide is usually grown on the back of the CIS wafer. At present, loo...

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Problems solved by technology

However, due to the inherent characteristics of furnace tube growth, three 20*20mm standoffs 1 are required to support the wafer. The positions of the three support points 1 are in close contact with the back of the wafer, and silicon nitride cannot be grown, such as figure 1 As shown, the low-temperature silicon dioxide at the positions of the three standoffs 1 on the back of the wafer in the subsequent etching is exposed to the etching plasma

[0006] The low-temperature silicon dioxide material on the back is loose, and it is easy to be bombarded by plasma to produce silicon oxide. Under the flow of cooling helium gas on the back of the wafer, it will be driven and dropped on the surface of the wafer, causing online defects and affecting the yield.

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