Semiconductor packaging body and manufacturing method thereof

Abstract

The invention provides a semiconductor packaging body and a manufacturing method thereof. The semiconductor packaging body comprises an insulating layer, a chip, a thermal interface material, a heat radiation cover body and a reconfiguration line layer, and is characterized in that the insulating layer is provided with an accommodating opening; the chip is arranged in the accommodating opening; the chip is provided with an active surface, a back surface opposite to the active surface, and a side surface connecting the active surface and the back surface; the thermal interface material fills the accommodating opening so as to at least coat the side surface of the chip and exposes the active surface; the reconfiguration line layer and the heat radiation cover body are respectively configured at two sides of the insulating layer; the heat radiation cover body is thermally coupled to the chip through the thermal interface material; and the reconfiguration line layer covers the active surface of the chip and the thermal interface material, and the reconfiguration line layer is electrically connected with the chip. The semiconductor packaging body provided by the invention has excellent heat radiation efficiency.

Description

technical field [0001] The present invention relates to a packaging body and its manufacturing method, and in particular to a semiconductor packaging body and its manufacturing method. Background technique [0002] In order to meet the requirements of light, thin and small electronic products, semiconductor packages, which are the core components of electronic products, are also developing in the direction of miniaturization. In recent years, the industry has developed a chip-scale package (Chip Scale Package, CSP for short) miniaturized semiconductor package, which is characterized in that the size of the aforementioned chip-scale package is approximately equal to the size of its chip or slightly larger than the size of its chip. size. On the other hand, in addition to miniaturization in size, the semiconductor package also needs to improve the integration (integrity) and the input / output terminals (Input / Output, referred to as I / O) for electrical connection with external ...

AI Technical Summary

Problems solved by technology

Generally speaking, the thickness of the encapsulant formed by the compression molding process is relatively thick, which is not conducive to the miniaturization of the wafer-level chip size package.

In addition, due to the low thermal conductivity and poor heat dissipation effect of the encapsulant, most of the heat generate

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