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A method for controlling etching depth of ultra-low-k dielectric material

A technology of etching depth and control method, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problem of inability to control the etching depth with time, and achieve the effect of meeting process requirements

Active Publication Date: 2019-05-14
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for controlling the etching depth of ultra-low K dielectric materials, which is used to solve the problem of etching gas in the prior art during the process of etching ultra-low K dielectric materials. The problem that the etching depth cannot be controlled by time

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  • A method for controlling etching depth of ultra-low-k dielectric material
  • A method for controlling etching depth of ultra-low-k dielectric material
  • A method for controlling etching depth of ultra-low-k dielectric material

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Embodiment Construction

[0026] The following describes the implementation of the present invention through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] Please refer to the attached picture. It should be noted that the diagrams provided in this embodiment only illustrate the basic idea of ​​the present invention in a schematic manner. The figures only show the components related to the present invention instead of the number, shape, and shape of the components in actual implementation. For size drawing, the type, quantity, and proportion of each component can be changed at will dur...

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Abstract

The invention provides an ultralow K medium material etching depth control method. The ultralow K medium material etching depth control method comprises: a gas flow of etching gas on an etcher is set; the etching gas is utilized to etch the ultralow K medium material layer on a wafer; an etching depth of the ultralow K medium material layer of the wafer is measured; an APC system determines whether the etching depth is deviated from a target depth according to the measured etching depth; if the etching depth is deviated from the target depth, the APC system outputs a regulated gas flow parameter; and the etcher regulates the etching gas flow according to the parameter, which enables the etching depth of the next wafer to be closer to the target depth. The ultralow K medium material etching depth control method can regulate the etching gas flow on a machine table through an APC feedback, can change the etching depth of the ultralow K medium material through etching difference between the wafers and enables the etching depth to satisfy the technology requirements.

Description

Technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for controlling the etching depth of ultra-low-K dielectric materials. Background technique [0002] As the node of complementary metal oxide semiconductor (CMOS) devices is reduced to 28nm and below, in the current back-end process of semiconductor manufacturing, in order to connect various components to form an integrated circuit, metal materials with relatively high conductivity such as copper are usually used. Wiring, that is, metal wiring. The conductive plugs are usually used for connection between metal wiring. The structure used to connect the active area of ​​the semiconductor device with other integrated circuits is generally a conductive plug. [0003] When the feature size reaches below the deep sub-micron process, when making copper wiring or conductive plugs, ultra-low-k (ULK) dielectric materials must be used as the dielectric layer (the ultra-low k i...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/311H01L21/67
CPCH01L21/31116H01L21/67253H01L21/76801
Inventor 孙武李莉杨乐
Owner SEMICON MFG INT (SHANGHAI) CORP