A differential bit line structure for flash memory and its operation method

Abstract

The present invention relates to a differential bit line structure of a flash memory and an operation method thereof, wherein the advantages of reliable reading, low program operation voltage, and long service life of storage units are realized. The structure comprises a pair of differential bit lines, and a data buffer circuit. The pair of differential bit lines include a first bit line BL0 and a second bit line BL1, wherein one ends of the first bit line BL0 and the second bit line BL1 are respectively connected to the data buffer circuit. The output end of the data buffer circuit is respectively connected to an output data line DQ and an output reverse data line DQB. The other end of the first bit line BL0 is connected with a first storage unit Cell 0. The other end of the second bit line BL1 is connected with a second storage unit Cell 1. The first storage unit Cell 0 and the second storage unit Cell 1 are different in threshold and collectively represent the information of one bit. When the first storage unit Cell 0 is high in threshold and the second storage unit Cell 1 is low in threshold, data are represented as 0 or 1. Otherwise, data are represented as 1 or 0.

Description

technical field [0001] The invention relates to the field of flash memory circuits, in particular to a differential bit line structure for the flash memory and an operation method thereof. Background technique [0002] Flash memory is a common non-volatile memory, and its characteristic is that even if the power supply is stopped, the data in the memory can still be kept for a long time. It is widely used in mobile storage, mobile phones, digital cameras, handheld computers and other digital devices. [0003] The basic operations of Flash memory include reading (read), programming (program) and erasing (erase). Both the erasing and programming of the Flash memory use the tunnel effect to allow electrons to pass through the insulating layer between the floating gate and the channel, and charge (write data) or discharge (erase data) to the floating gate. The amount of charge on the floating gate will affect the threshold voltage of the Flash memory cell. The reading of the ...

AI Technical Summary

Problems solved by technology

[0007] The disadvantages of using this method are: 1. Due to the need for a certain margin between the BL voltage representing data 1 and 0 and the reference voltage during the read operation, it is necessary to wait for a long bit line discharge time

2. In order to make the threshold value of the programmed memory cell higher during the programming operation, the voltage required will be higher and longer, which will cause greater interference and reduce the life of the entire memory

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