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Bump structure, packaging assembly and bump structure forming method

A technology of packaging components and bumps, which is applied in the direction of electrical components, electrical solid devices, semiconductor devices, etc., can solve problems such as short circuit, increase production cost, and device damage, and achieve the effects of reducing production cost, avoiding short circuit, and small size

Active Publication Date: 2017-03-08
SJ SEMICON JIANGYIN CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the pitch of the conductive traces is very small, adjacent raised structures can contact each other and cause a short circuit, causing damage to the device
In order to avoid short circuits, the spacing of conductive traces in existing flip-chip packages must be kept at sufficient spacing, which limits the miniaturization of the device size, which in turn increases the production cost

Method used

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  • Bump structure, packaging assembly and bump structure forming method
  • Bump structure, packaging assembly and bump structure forming method
  • Bump structure, packaging assembly and bump structure forming method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0069] see image 3 , the present invention provides a bump structure, the bump structure 21 includes: a conductive pillar 211, the top of the conductive pillar 211 is formed with a concave surface; a covering layer 212, the covering layer 212 covers the top of the conductive pillar 211 ; The solder layer 213, the solder layer 213 is located on the cover layer 212 in the concave surface.

[0070] As an example, the width of the concave surface can be set according to actual needs, and the width of the concave surface can be smaller than or equal to the width of the conductive column 211. Preferably, in this embodiment, the width of the concave surface is smaller than the width of the conductive column 211. The width of the column 211.

[0071] As an example, the concave surface is located at the center of the conductive pillar 211 , that is, the central line of the concave surface coincides with the central line of the conductive pillar 211 .

[0072] As an example, the shap...

Embodiment 2

[0082] see Figure 4 , the present invention also provides a packaging assembly, which includes: a first substrate 22, the surface of the first substrate 22 is provided with a metal pad 23; the bump structure 21 as described in Embodiment 1, the The bump structure 21 is located on the metal pad 23; the second substrate (not shown), the surface of the second substrate is provided with conductive traces 25; the bump structure 21 is pasted on the solder layer 213 on the conductive trace 25 .

[0083] As an example, the surface of the first base 22 is further provided with a passivation layer 24, the passivation layer 24 covers the surface of the first base 22, and an opening is formed at a position corresponding to the metal pad 23, The UBM layer 214 in the bump structure 21 is connected to the metal pad 23 through the opening.

[0084] The structure and characteristics of the bump structure 21 in this embodiment are exactly the same as those of the bump structure 21 in the fir...

Embodiment 3

[0087] see Figure 5 , the present invention also provides a method for forming a bump structure, the method for forming a bump structure includes:

[0088] S1: provide a substrate;

[0089] S2: forming an under bump metallurgy layer on the base body;

[0090] S3: forming a conductive column with a concave surface on the top of the UBM layer through an electroplating process;

[0091] S4: forming a covering layer on the top of the conductive pillar;

[0092] S5: forming a solder layer on the covering layer located in the concave surface.

[0093] In step S1, see Figure 5 In step S1, a substrate is provided.

[0094] As an example, the substrate may be any existing semiconductor substrate.

[0095] In step S2, see Figure 5 In step S2, an under bump metallurgy layer is formed on the substrate.

[0096] As an example, the UBM layer can be formed on the substrate by using processes such as deposition and electroplating. Preferably, in this implementation, the UBM layer i...

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Abstract

The invention provides a bump structure, a packaging assembly and a bump structure forming method. The bump structure comprises a conductive pillar which is provided with a concave surface on the top, a cover layer which covers the top of the conductive pillar, and a solder layer which is disposed on the cover layer in the concave surface. By forming the concave surface on the top of the conductive pillar and arranging the solder layer in the concave surface, the solder layer is limited in the concave surface after a flip chip solder reflow process even at high temperature, the solder layer does not protrude to the two sides of the conductive pillar from the original position, and short circuit caused by contact of adjacent solder layers is avoided effectively. A flip chip package can be smaller and lighter, and the production cost can be reduced.

Description

technical field [0001] The invention belongs to the field of semiconductor packaging, and in particular relates to a bump structure, a packaging component and a forming method thereof. Background technique [0002] Bump structures have been widely used in flip-chip packaging processes in which the bump structures are directly bonded to conductive traces in the package substrate. As the internal connection structure of the flip-chip package, the bump structure has the characteristics of high connection density, small package size, and good electrical and thermal properties. [0003] Bump structures in the prior art such as figure 1 As shown, the bump structure 11 includes an UBM layer 114, a copper pillar 111 on the UBM layer 114, a Ni layer 112 on the copper pillar 111, and a Ni layer 112 on the Ni layer 112. SnAg layer 113 on top; the bump structure 11 is set on the metal pad 13 on a base 12 through the under bump metal layer 114, and the surface of the base 12 is provide...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/488H01L23/485H01L21/60
CPCH01L2224/11
Inventor 林正忠蔡奇风
Owner SJ SEMICON JIANGYIN CORP