ATE-based method for testing FPGA configuration chip

Abstract

The invention provides an ATE-based method for testing an FPGA configuration chip. The method is characterized in that the method includes setting values of a device working power supply, an input level, an output level, a reference level and a load current, setting a powering-on order of a device, data formats, a time sequence and channels of an address signal, control signal and data signal of the device and controlling allocation of registers, performing erasure and verification of a full chip, erasure and verification of a single sector, writing state register verification, chip ID reading verification, reading and writing function verification of a full-chip memory cell, writing protection verification, direct current parameter verification and alternating current parameter verification. According to the ATE-based method for testing the FPGA configuration chip proposed by the invention, based on a T5385ES super-large-scale integrated circuit memory test system, compiles a special test pattern aiming at EPCS16SI8N, completes testing of EPCS16SI8N, and detects a possible failure mode of the EPCS16SI8N.

Description

technical field [0001] The invention relates to the technical field of integrated circuit testing, in particular to a testing method for an ATE-based FPGA configuration chip. Background technique [0002] EPCS16SI8N is a large-capacity, serial-port FPGA configuration chip from ALTERA, with a total capacity of 16Mbit and a total of 32 sectors. Each sector contains 256 pages, and each page contains 256 Bytes. The operating voltage range is from 2.7V to 3.6 V, the maximum operating current is 15mA, the maximum quiescent current is 50uA, the maximum operating frequency is 25MHz, and the package is SOIC-8. [0003] Memory testing is usually based on the fault model of the storage unit. Common fault models mainly include (1) fault model based on fixed cells; (2) memory test fault model based on bridging defects; (3) memory test based on associated defects Fault model; (4) decoding fault model; (5) data storage fault model, etc. The failure modes exhibited by these failure mode...

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a kind of test method based on FPGA configuration chip of ATE, t...