Chip packaging structure and preparation method thereof

Abstract

The invention discloses a chip packaging structure and a preparation method thereof. The preparation method comprises the following steps: providing a support plate, and preparing double-layer peeling structures on the upper surface and the lower surface of the support plate; preparing a rewiring layer on the side, away from the support plate, of each double-layer peeling structure; preparing first dielectric layers on each rewiring layer and the surface of each double-layer peeling structure; preparing at least one blind hole in each first dielectric layer; filling a conducting material in the blind holes; providing a chip, and arranging the chip on each first dielectric layer; preparing a second dielectric layer on the periphery of each chip, wherein each first dielectric layer is covered with the corresponding second dielectric layer, and each chip is wrapped by the corresponding second dielectric layer; peeling off the double-layer peeling structures; etching an upper-layer structure of each double-layer peeling structure so as to expose the corresponding rewiring layer and the corresponding first dielectric layer; and preparing a welded ball on the side, away from each first dielectric layer, of the corresponding rewiring layer, wherein each welded ball is electrically connected with the corresponding rewiring layer. To sum up, the preparation method is simple, high in operability and low in cost, and can avoid chip damage; and moreover, preparation technology is carried out on two sides of the support plate simultaneously, so that the efficiency is high, and warping is avoided.

Description

technical field [0001] The embodiments of the present invention relate to the technical field of chip packaging, and in particular to a chip packaging structure and a manufacturing method thereof. Background technique [0002] With the continuous development of information technology and semiconductor technology, electronic devices such as mobile phones, PADs, and smart watches are gradually showing a trend of light weight and integrated functions. This has higher and higher requirements for the integration of chips in electronic equipment, which in turn brings unprecedented challenges to chip packaging. Increasing interconnect pitch mismatches, adding various chips with different functions, and reducing package size in the same footprint to increase battery size for longer life have opened windows for innovative embedded packaging technologies. [0003] Benefiting from the development of 3D Through Silicon Vias (TSV) technology, Fan-Out Wafer Level Packaging (FOWLP) is cur...

AI Technical Summary

Problems solved by technology

[0005] In view of this, an embodiment of the present invention provides a chip packaging structure and a manufacturing method thereof, so as to solve the technical problems of high cost, chip damage, and warpage in the manufacturing process of the existing fan-out chip

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