Method and circuit using low voltage device to realize ESD protection of high voltage circuit

Abstract

The invention discloses a method and circuit using low voltage devices to realize ESD protection of a high voltage circuit; the method comprises the following steps: forming a charging current when a capacitor C0 receives an ESD pulse, forming voltage drop on a resistor R0, and controlling a second PMOS transistor MP1 and a third PMOS transistor to open; when the output voltage outputted by the second PMOS transistor MP1 and a first NMOS transistor MN0 is high level, and the bias voltage Vb2 outputted by the third PMOS transistor MP2 and the first PMOS transistor MP0 is high level, the third NMOS transistor MN2 and the second NMOS transistor MN1 are opened to release current. The method and circuit can improve the chip ESD protection ability, thus ensuring chip yield and reliability.

Description

technical field [0001] The invention belongs to the technical field of circuits, and in particular relates to a method and a circuit for realizing ESD protection for high-voltage circuits based on low-voltage devices. Background technique [0002] Electrostatic discharge (Electro Static Discharge, ESD) refers to the event that a limited charge is transferred between two objects that are close together and have different electrostatic potentials. The rise and fall of current and potential caused by this event is the study of electrostatic discharge main object. [0003] In the semiconductor industry, there are a large number of chip failures caused by electrostatic discharge phenomena. According to statistics, chip failures caused by ESD account for about 30% to 50% of the total number of chip failures. During the chip production process, transportation process, and even the system integration stage and user use stage, all these processes may generate electrostatic discharge...

AI Technical Summary

Problems solved by technology

During the production process of the chip, the transportation process, and even the system integration stage and the user use stage, all these processes may generate electrostatic discharge on its pins, causing the chip to fail.

The instantaneous high-current pulse generated by ESD flows through the chip pins through the chip, which will cause damage to the internal circuit of the chip and cause it to fail to work normally.

In addition, the ESD damage suffered by some chips is potential, which is often referred to as soft failure. This type of failure is usually difficult to find in the testing phase, but when the final product is delivered to the end user, the use of the product Life expectancy will be greatly reduced

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