CMOS clock generator

Abstract

The invention discloses a CMOS clock generator comprising a current generation unit, a periodic signal generation unit, a voltage negative feedback unit, and a square wave signal generation unit. The current generation unit connected with an external power supply, the periodic signal generation unit and the voltage negative feedback unit respectively provides working currents for the periodic signal generation unit and the voltage negative feedback unit; the periodic signal generation unit connected with the voltage negative feedback unit and the square wave signal generation unit generates a periodic ramp signal; the square wave signal generation unit connected with the voltage negative feedback unit converts the periodic ramp signal into a square wave signal and outputs a clock signal; and the voltage negative feedback unit is used for adjusting the cycle of the periodic ramp signal generated by the periodic signal generation unit. Because the clock cycle of the clock signal generated by the CMOS clock generator is independent of delay of a comparator, the temperature coefficient can be reduced and the accuracy of the clock cycle can be improved.

Description

technical field [0001] The present invention relates to the field of integrated circuits, more specifically to a CMOS clock generator. Background technique [0002] refer to figure 1 , the CMOS clock generator of prior art is made up of three parts: by MOS tube M1, M2, M3, the electric current generation unit that resistance R1 forms; By MOS tube M4, M5, M6, M7, M8, M9, resistance R2 , a periodic signal generation unit composed of capacitors C1 and C2, wherein the capacitors C1 and C2 are capacitors with identical specifications and parameters, and their capacitance values ​​are both C. A square wave generation unit composed of a comparator CMP1 and an inverter INV1. [0003] Assuming that the current flowing through the MOS transistor M1 is I1 in the CMOS clock generator of the prior art, the current I1 is: [0004] I1=Vd1 / R1 [0005] Wherein, Vd1 is the drain node voltage of the MOS transistor M1. [0006] The MOS transistors M1 , M2 and M3 form a current mirror struc...

AI Technical Summary

Problems solved by technology

In the CMOS process, the delay of the comparator will change greatly with the change of temperature (especially in low-power applications), and this change will directly affect the size of the clock cycle, reducing the generated clock cycle. the accuracy of

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