ADC chip circuit based on gate voltage bootstrap circuit and segmented full capacitor array

Abstract

The invention provides an ADC chip circuit based on gate voltage bootstrap circuit and segmented full capacitor array. According to the circuit, a clock signal is generated through the CLK signal generation circuit required for the internal conversion work of a chip; a switch circuit conducts sampling to the external signals, connects external signals with the DAC capacitor array as well as saves the sampled signals into the DAC; the sampled signals saved in the DAC capacitor array perform charge release under the control of an SAR logic circuit so as to reach required electric level signals; the charge signals saved in the DAC are used as input signals for a comparator; the comparator compares the differential electric level signals saved in the DAC capacitor array to obtain the zero level signals or the VDD power level signals; the signals obtained from the comparison are used as the signal source for generating a clock signal for the internal conversion work of a chip in addition to be outputted to the external part of the chip. In this manner, the precise control over the outputted electric levels of a DAC capacitor array is realized.

Description

technical field [0001] The invention relates to the technical field of digital-to-analog conversion, and more specifically, to an ADC chip circuit based on a grid voltage bootstrap circuit and a segmented full capacitor array. Background technique [0002] In the Internet of Things, data acquisition is the entrance of the entire Internet of Things application, and the digital-to-analog converter (ADC) converts the continuous time signal into a discrete digital signal for signal processing. The analog-to-digital converter is completed during the entire acquisition process. The most important peripheral for this task. At the same time, there are a large number of nodes and interfaces in the Internet of Things, so the power consumption of each node should be as small as possible. ADCs with low power consumption are widely used in various acquisition devices. [0003] In the current ADC design, successive approximation (SAR), pipeline (Pipeline), and oversampling (Oversample) ...

AI Technical Summary

Problems solved by technology

[0004] In the existing technology, the power consumption of the ADC is usually relatively large, and the power consumption of the ADC with 10-bit precision generally reaches tens of milliwatts.

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