Partial-scan trigger selection optimizing method based on integer programming model

Abstract

The invention discloses a partial-scan trigger selection optimizing method based on an integer programming model; the method comprises the main steps of first, integrating circuits to generate a netlist; second, using netlist analysis software to generate a circuit graph model; generating an integer programming problem according to the graph model; third, solving integer programming to obtain partial-scan results, and inserting a scan chain; fourth, outputting a chart. The number of partial-scan triggers is decreased at the premise of maintaining complete observability and controllability of circuitry, so that area resource consumption due to the scan chain is reduced and the cost of FPGA (field programmable gate array) hardware simulation is reduced.

Description

technical field [0001] The invention relates to the testability design optimization of an integrated circuit, in particular to a partial scan optimization for an FPGA hardware simulation platform. Background technique [0002] Design for testability is critical to improving the observability and controllability of circuits. Design for testability generally uses scan flip-flops to replace common flip-flops. Compared with ordinary flip-flops, the scan flip-flop has an extra multiplexer at its data input, and the selection signal of the selector determines whether the flip-flop works in normal mode or scan mode. In normal mode, the circuit operates as intended and the flip-flop's input is connected to normal data. In scan mode, the flip-flops in the circuit are connected back and forth, and the input of the scan flip-flop is connected to the output of the upper-stage scan flip-flop. All the flip-flops form a shift register, which can scan a specific bit sequence into the cir...

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Problems solved by technology

[0004] The object of the present invention is to propose a partial scan flip-flop selection optimization method based on an integer programming model, to overcome the shortcomings of excessive consumption of area resources caused by inserting scan chains on the FPGA hardware simulation platform, and to maintain the completeness of the circuit. Under the premise of observability and controllability, the number of partial scan flip-flops is reduced, thereby reducing the area resource consumption caused by the scan chain and reducing the cost of FPGA hardware simulation

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