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Semiconductor packaging structure and processing method

A technology of packaging structure and processing method, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problem of chip electrodes affecting installation, and achieve the effect of preventing short circuit

Inactive Publication Date: 2017-05-24
GREAT TEAM BACKEND FOUNDRY (DONGGUAN) LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Another object of the present invention is to provide a semiconductor packaging structure, which can solve the problem that the chip electrodes are located on different planes and affect the installation.

Method used

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  • Semiconductor packaging structure and processing method
  • Semiconductor packaging structure and processing method
  • Semiconductor packaging structure and processing method

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Effect test

Embodiment 1

[0049] Such as Figure 1-14 As shown, in this embodiment, a semiconductor package structure according to the present invention includes a chip 1, the chip 1 has a first surface and a second surface opposite to the first surface, the first surface And the second surface is provided with electrodes, the position corresponding to the first surface and the electrode is covered with solder paste 2, and the rest of the position is covered with plastic sealing material 3, the outer surface of the solder paste 2 and the plastic sealing material 3 The surface forms the packaging surface, and the second surface directly connects the electrical connections.

[0050] In this embodiment, the electrodes provided on the first surface are the source 11 and the gate 12 , and the electrodes provided on the second surface are the drain. The thickness of the solder paste 2 covering the source electrode 11 and the gate electrode 12 is the same as the thickness of the molding material 3 used to pa...

Embodiment 2

[0064] Such as Figure 3-10 , 15-18, in this embodiment, a semiconductor package structure according to the present invention includes a chip 1, the chip 1 has a first surface and a second surface opposite to the first surface, the Both the first surface and the second surface are provided with electrodes, the positions corresponding to the first surface and the electrodes are covered with solder paste 2, and the rest of the positions are covered with plastic packaging material 3, the solder paste 2 and the plastic packaging The outer surface of the material 3 forms the encapsulation surface, said second surface directly connecting the electrical connections.

[0065] The molding material 3 covered on the first surface has the same thickness as the solder paste 2 . The chip 1 is fixedly connected to the electrical connector through a conductive bonding material 6 . The electrodes provided on the first surface are the source 11 and the gate 12 , and the electrodes provided on...

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PUM

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Abstract

The invention discloses a semiconductor packaging structure, which comprises a chip, wherein the chip comprises a first surface and a second surface opposite to the first surface, the first surface and the second surface are provided with electrodes, the first surface is coated with a solder paste at positions corresponding to the electrodes, the rest of the first surface is coated with a plastic packaging material, the solder paste and the outer surface of the plastic packaging material form a packaging surface, and the second surface is directly connected with an electrical connector. The invention further discloses a processing method of the semiconductor packaging structure. According to the processing method, a lead wire frame is arranged to be connected with a drain of the second surface, and a drain end is led to the same plane as a source and a gate by means of the lead wire frame, thereby being conductive to welding the chip on a PCB. Since the first surface provided with the source and the gate is close to the drain on a frame flanging, an insulating material is arranged between the chip and the frame flanging, thereby being capable of effectively preventing short circuit caused by voltage breakdown.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor packaging structure and a processing method for the semiconductor packaging structure. Background technique [0002] With the development of wireless communication technology, the complexity of wireless communication systems increases rapidly, and various mobile communication networks coexist, such as 2G, 3G and 4G mobile communication networks that are widely used now. In addition, people also hope that the functions of the mobile terminal will become thinner or smaller at the same time. Therefore, these demands have higher and higher requirements for the performance and integration of integrated circuits in mobile terminals, higher operating speed and power consumption, and higher requirements for packaging structures, especially stricter requirements for packaging heat dissipation. . [0003] In order to realize the electrical connection between the pa...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31H01L23/492H01L23/498H01L21/56H01L21/60
CPCH01L2224/0603H01L21/56H01L23/31H01L23/492H01L23/498
Inventor 曹周徐振杰
Owner GREAT TEAM BACKEND FOUNDRY (DONGGUAN) LTD