Method for manufacturing field effect transistor of fin-type metal oxide semiconductor

Abstract

The invention provides a method for manufacturing a field effect transistor of a fin-type metal oxide semiconductor. The method comprises the steps of providing a substrate and forming a shallow trench isolation, a fin structure, a gate structure and an internal offset side wall on the substrate; forming a first layer of epitaxial source-drain region EpiSD on the fin structure at two sides of the internal offset side wall; forming a first layer of outer side wall above the first layer of epitaxial source-drain region and two sides of the internal offset side wall; further forming a second layer of epitaxial source-drain region on the first layer of epitaxial source-drain region at two sides of the first layer of outer side wall; and further forming a second layer of outer side wall at two sides of the first layer of outer side wall above the second layer of epitaxial source-drain region, repeating the operation may times to form the epitaxial source-drain regions and the outer side walls, and finally forming a stepped side wall and epitaxial source-drain region structure, wherein the total thickness of required raised source-drain regions is the sum of all epitaxial source-drain regions and the thicknesses of all epitaxial source-drain regions, and the total thickness of the outer side walls is the sum of all outer side walls and the thicknesses of all outer side walls.

Description

technical field [0001] The present invention relates to the technical field of manufacturing semiconductor integrated circuits, and more specifically, relates to a method for manufacturing a low parasitic capacitance Fin-type Metal Oxide Semiconductor Field Effect Transistor (FinFET) with a stepped side wall (Spacer) structure. Background technique [0002] In the field of modern integrated circuit technology, after entering the 90nm process era, with the substantial reduction in the size of integrated circuit devices, the junction depth of the source and drain is getting shallower and shallower, and selective epitaxy (SEG) is required to thicken the source and drain. The pole (elevated source / drain) is used as a sacrificial layer (sacrificial layer) for the subsequent silicide reaction, thereby reducing the series resistance. For 65 / 45nm and smaller technology node processes, the industry generally adopts the epitaxial SiGe layer after etching the source and drain of PMOS t...

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Problems solved by technology

However, this method requires a sloped notch at the bottom of its final exterior wall structure to balance the trade-off between resistance and parasitic capacitance

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